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Tue, 5 Nov 2019 21:25:32 +0000 From: "Moger, Babu" To: "tglx@linutronix.de" , "mingo@redhat.com" , "bp@alien8.de" , "hpa@zytor.com" , "pbonzini@redhat.com" , "rkrcmar@redhat.com" , "sean.j.christopherson@intel.com" , "vkuznets@redhat.com" , "wanpengli@tencent.com" , "jmattson@google.com" CC: "x86@kernel.org" , "joro@8bytes.org" , "Moger, Babu" , "luto@kernel.org" , "zohar@linux.ibm.com" , "yamada.masahiro@socionext.com" , "nayna@linux.ibm.com" , "linux-kernel@vger.kernel.org" , "kvm@vger.kernel.org" , "zohar@linux.ibm.com" , "yamada.masahiro@socionext.com" , "ebiederm@xmission.com" , "ricardo.neri-calderon@linux.intel.com" , "bshanks@codeweavers.com" Subject: [PATCH v3 1/2] x86/Kconfig: Rename UMIP config parameter Thread-Topic: [PATCH v3 1/2] x86/Kconfig: Rename UMIP config parameter Thread-Index: AQHVlB+O3ASEuWoCTkuU8z7yyrBiRA== Date: Tue, 5 Nov 2019 21:25:32 +0000 Message-ID: <157298912544.17462.2018334793891409521.stgit@naples-babu.amd.com> References: <157298900783.17462.2778215498449243912.stgit@naples-babu.amd.com> In-Reply-To: <157298900783.17462.2778215498449243912.stgit@naples-babu.amd.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: SN6PR04CA0059.namprd04.prod.outlook.com (2603:10b6:805:2a::36) To DM5PR12MB2471.namprd12.prod.outlook.com (2603:10b6:4:b5::10) authentication-results: spf=none (sender IP is ) smtp.mailfrom=Babu.Moger@amd.com; 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received-spf: None (protection.outlook.com: amd.com does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 x-microsoft-antispam: BCL:0; x-microsoft-antispam-message-info: ClSbpkyoYOR8wv0hOslz+teUZvAaJ0bhbL1mAd/teMgxh4jPhn+muqf7IvBt/MB8AVjhZx/7rzk3wNBVTnvJcx8bnXzUSeoHRYB8kEMsMMWKEaFlLFv1ucYDavJZpBzcBxlzcYF4YrX6kSmAdCFWZo4P7laEebnnx4w5qwpB8rGQEI5zfJfbVRHAfZLxPWCVKDD/FybvamVJpoZMOuWgYnMWJU2W0ztnEy32wlQsm2ioMW0XexLak2Fq2g5L4He4YbQwvtNSntSkB5hUu2Yti+NlZuRecHm5ZSKIdoyRFWufqR5N+F1YQZmkh5lUNQgezlrofL/kOdiV4LwY0c/PHUOeCeOBkScZjlLo/2xaKovHR4FWL4B4+iS64xBRx8h0lLN9FckzjKypD6P4hhVEDtqnLNLuytDIWHlqgKjNC20yhrSrTvSaHLUV6CA2yhCO Content-ID: MIME-Version: 1.0 X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-Network-Message-Id: f1b24793-9b72-4653-0924-08d76236b06a X-MS-Exchange-CrossTenant-originalarrivaltime: 05 Nov 2019 21:25:32.6178 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: e0feHaupNd+ZncqL/7giuXPSjEoF7LB9RTQgGcVk3ySvPm9S+mfW/oEfmg125hyN X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM5PR12MB1195 Sender: kvm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org AMD 2nd generation EPYC processors support the UMIP (User-Mode Instruction Prevention) feature. So, rename X86_INTEL_UMIP to generic X86_UMIP and modify the text to cover both Intel and AMD. Signed-off-by: Babu Moger --- arch/x86/Kconfig | 10 +++++----- arch/x86/include/asm/disabled-features.h | 2 +- arch/x86/include/asm/umip.h | 4 ++-- arch/x86/kernel/Makefile | 2 +- 4 files changed, 9 insertions(+), 9 deletions(-) diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index d6e1faa28c58..b7fb285d7c0f 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -1880,13 +1880,13 @@ config X86_SMAP If unsure, say Y. -config X86_INTEL_UMIP +config X86_UMIP def_bool y - depends on CPU_SUP_INTEL - prompt "Intel User Mode Instruction Prevention" if EXPERT + depends on CPU_SUP_INTEL || CPU_SUP_AMD + prompt "User Mode Instruction Prevention" if EXPERT ---help--- - The User Mode Instruction Prevention (UMIP) is a security - feature in newer Intel processors. If enabled, a general + User Mode Instruction Prevention (UMIP) is a security + feature in newer x86 processors. If enabled, a general protection fault is issued if the SGDT, SLDT, SIDT, SMSW or STR instructions are executed in user mode. These instructions unnecessarily expose information about the hardware state. diff --git a/arch/x86/include/asm/disabled-features.h b/arch/x86/include/asm/disabled-features.h index a5ea841cc6d2..8e1d0bb46361 100644 --- a/arch/x86/include/asm/disabled-features.h +++ b/arch/x86/include/asm/disabled-features.h @@ -22,7 +22,7 @@ # define DISABLE_SMAP (1<<(X86_FEATURE_SMAP & 31)) #endif -#ifdef CONFIG_X86_INTEL_UMIP +#ifdef CONFIG_X86_UMIP # define DISABLE_UMIP 0 #else # define DISABLE_UMIP (1<<(X86_FEATURE_UMIP & 31)) diff --git a/arch/x86/include/asm/umip.h b/arch/x86/include/asm/umip.h index db43f2a0d92c..aeed98c3c9e1 100644 --- a/arch/x86/include/asm/umip.h +++ b/arch/x86/include/asm/umip.h @@ -4,9 +4,9 @@ #include #include -#ifdef CONFIG_X86_INTEL_UMIP +#ifdef CONFIG_X86_UMIP bool fixup_umip_exception(struct pt_regs *regs); #else static inline bool fixup_umip_exception(struct pt_regs *regs) { return false; } -#endif /* CONFIG_X86_INTEL_UMIP */ +#endif /* CONFIG_X86_UMIP */ #endif /* _ASM_X86_UMIP_H */ diff --git a/arch/x86/kernel/Makefile b/arch/x86/kernel/Makefile index 3578ad248bc9..52ce1e239525 100644 --- a/arch/x86/kernel/Makefile +++ b/arch/x86/kernel/Makefile @@ -134,7 +134,7 @@ obj-$(CONFIG_EFI) += sysfb_efi.o obj-$(CONFIG_PERF_EVENTS) += perf_regs.o obj-$(CONFIG_TRACING) += tracepoint.o obj-$(CONFIG_SCHED_MC_PRIO) += itmt.o -obj-$(CONFIG_X86_INTEL_UMIP) += umip.o +obj-$(CONFIG_X86_UMIP) += umip.o obj-$(CONFIG_UNWINDER_ORC) += unwind_orc.o obj-$(CONFIG_UNWINDER_FRAME_POINTER) += unwind_frame.o