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[v3,2/2] x86/umip: Update the comments to cover generic x86 processors

Message ID 157298913784.17462.12654728938970637305.stgit@naples-babu.amd.com (mailing list archive)
State New, archived
Headers show
Series Update UMIP config parameter and docs | expand

Commit Message

Moger, Babu Nov. 5, 2019, 9:25 p.m. UTC 
AMD 2nd generation EPYC processors also support UMIP feature.
Update the comments to cover generic x86 processors.

Signed-off-by: Babu Moger <babu.moger@amd.com>
---
 arch/x86/kernel/umip.c |   12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)
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Patch

diff --git a/arch/x86/kernel/umip.c b/arch/x86/kernel/umip.c
index 548fefed71ee..8ccef6c495dc 100644
--- a/arch/x86/kernel/umip.c
+++ b/arch/x86/kernel/umip.c
@@ -1,6 +1,6 @@ 
 /*
- * umip.c Emulation for instruction protected by the Intel User-Mode
- * Instruction Prevention feature
+ * umip.c Emulation for instruction protected by the User-Mode Instruction
+ * Prevention feature
  *
  * Copyright (c) 2017, Intel Corporation.
  * Ricardo Neri <ricardo.neri-calderon@linux.intel.com>
@@ -18,10 +18,10 @@ 
 
 /** DOC: Emulation for User-Mode Instruction Prevention (UMIP)
  *
- * The feature User-Mode Instruction Prevention present in recent Intel
- * processor prevents a group of instructions (SGDT, SIDT, SLDT, SMSW and STR)
- * from being executed with CPL > 0. Otherwise, a general protection fault is
- * issued.
+ * User-Mode Instruction Prevention is a security feature present in recent
+ * x86 processors that, when enabled, prevents a group of instructions (SGDT,
+ * SIDT, SLDT, SMSW and STR) from being run in user mode by issuing a general
+ * protection fault if the instruction is executed with CPL > 0.
  *
  * Rather than relaying to the user space the general protection fault caused by
  * the UMIP-protected instructions (in the form of a SIGSEGV signal), it can be