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Tue, 5 Nov 2019 21:25:40 +0000 From: "Moger, Babu" To: "tglx@linutronix.de" , "mingo@redhat.com" , "bp@alien8.de" , "hpa@zytor.com" , "pbonzini@redhat.com" , "rkrcmar@redhat.com" , "sean.j.christopherson@intel.com" , "vkuznets@redhat.com" , "wanpengli@tencent.com" , "jmattson@google.com" CC: "x86@kernel.org" , "joro@8bytes.org" , "Moger, Babu" , "luto@kernel.org" , "zohar@linux.ibm.com" , "yamada.masahiro@socionext.com" , "nayna@linux.ibm.com" , "linux-kernel@vger.kernel.org" , "kvm@vger.kernel.org" , "zohar@linux.ibm.com" , "yamada.masahiro@socionext.com" , "ebiederm@xmission.com" , "ricardo.neri-calderon@linux.intel.com" , "bshanks@codeweavers.com" Subject: [PATCH v3 2/2] x86/umip: Update the comments to cover generic x86 processors Thread-Topic: [PATCH v3 2/2] x86/umip: Update the comments to cover generic x86 processors Thread-Index: AQHVlB+SCjh4NAufykaxQBgEbCDhKg== Date: Tue, 5 Nov 2019 21:25:40 +0000 Message-ID: <157298913784.17462.12654728938970637305.stgit@naples-babu.amd.com> References: <157298900783.17462.2778215498449243912.stgit@naples-babu.amd.com> In-Reply-To: <157298900783.17462.2778215498449243912.stgit@naples-babu.amd.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: SN4PR0401CA0011.namprd04.prod.outlook.com (2603:10b6:803:21::21) To DM5PR12MB2471.namprd12.prod.outlook.com (2603:10b6:4:b5::10) authentication-results: spf=none (sender IP is ) smtp.mailfrom=Babu.Moger@amd.com; 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received-spf: None (protection.outlook.com: amd.com does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 x-microsoft-antispam: BCL:0; x-microsoft-antispam-message-info: I+u+d79jUFisN2RQFOBONPb3+T9DF/HJGCU0KUkn84+UGiI8j6nbJLT3LjsCda522JFnIggrELevJYXig61WV3vSWf7oAR6GqLr35OLoxZMzmwtrHwOcKcFOQJQBajeHaDvp+iMfqy2OC4/nzMr1eh8x8/qNDqpbcpF8leE/2O3A218gRXgnCfNTxy0XKC9RGJ+pJiozuEGFvM5o8SqAUWe7oPq2eDupLKPZIE3uvbhkImKTEKlobJom8ZC7B9+q1zzBJeSnHC624FanQg8fs/5z4lqbPFyEmfd5Xcxs3NmKOxzps/6LFLlkarPjmB5Ogaf3jcXSRGV0YHYu56NZZDT8blQu8Xbyf+OZ7+n9lbFiOvc4A1AV4GaVq01iLsaYaWBaK1WHJDBBwPRpK7VbbXJ/AUGSbn8u5eR6RUUd21k+eWJeodYdKFH98Fah76JL Content-ID: MIME-Version: 1.0 X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-Network-Message-Id: 509a3f88-56e2-475c-3961-08d76236b4db X-MS-Exchange-CrossTenant-originalarrivaltime: 05 Nov 2019 21:25:40.0295 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: Oo9pSPkhWyfKskTEFYlzYIpRvIPQqtAv+9AcKVJPEktNKSMRdG+y/v70S3S35o9F X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM5PR12MB1195 Sender: kvm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org AMD 2nd generation EPYC processors also support UMIP feature. Update the comments to cover generic x86 processors. Signed-off-by: Babu Moger --- arch/x86/kernel/umip.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/x86/kernel/umip.c b/arch/x86/kernel/umip.c index 548fefed71ee..8ccef6c495dc 100644 --- a/arch/x86/kernel/umip.c +++ b/arch/x86/kernel/umip.c @@ -1,6 +1,6 @@ /* - * umip.c Emulation for instruction protected by the Intel User-Mode - * Instruction Prevention feature + * umip.c Emulation for instruction protected by the User-Mode Instruction + * Prevention feature * * Copyright (c) 2017, Intel Corporation. * Ricardo Neri @@ -18,10 +18,10 @@ /** DOC: Emulation for User-Mode Instruction Prevention (UMIP) * - * The feature User-Mode Instruction Prevention present in recent Intel - * processor prevents a group of instructions (SGDT, SIDT, SLDT, SMSW and STR) - * from being executed with CPL > 0. Otherwise, a general protection fault is - * issued. + * User-Mode Instruction Prevention is a security feature present in recent + * x86 processors that, when enabled, prevents a group of instructions (SGDT, + * SIDT, SLDT, SMSW and STR) from being run in user mode by issuing a general + * protection fault if the instruction is executed with CPL > 0. * * Rather than relaying to the user space the general protection fault caused by * the UMIP-protected instructions (in the form of a SIGSEGV signal), it can be