From patchwork Fri Dec 6 16:26:20 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pierre Morel X-Patchwork-Id: 11276777 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id C29FE17EF for ; Fri, 6 Dec 2019 16:26:38 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id A9D8C20659 for ; Fri, 6 Dec 2019 16:26:38 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726395AbfLFQ0h (ORCPT ); Fri, 6 Dec 2019 11:26:37 -0500 Received: from mx0a-001b2d01.pphosted.com ([148.163.156.1]:37850 "EHLO mx0a-001b2d01.pphosted.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726315AbfLFQ0g (ORCPT ); Fri, 6 Dec 2019 11:26:36 -0500 Received: from pps.filterd (m0098410.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id xB6GEoLl068873 for ; Fri, 6 Dec 2019 11:26:35 -0500 Received: from e06smtp05.uk.ibm.com (e06smtp05.uk.ibm.com [195.75.94.101]) by mx0a-001b2d01.pphosted.com with ESMTP id 2wq9g6c90b-1 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=NOT) for ; Fri, 06 Dec 2019 11:26:35 -0500 Received: from localhost by e06smtp05.uk.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! 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Violators will be prosecuted; (version=TLSv1/SSLv3 cipher=AES256-GCM-SHA384 bits=256/256) Fri, 6 Dec 2019 16:26:31 -0000 Received: from d06av21.portsmouth.uk.ibm.com (d06av21.portsmouth.uk.ibm.com [9.149.105.232]) by b06cxnps4074.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id xB6GQUi352232390 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Fri, 6 Dec 2019 16:26:30 GMT Received: from d06av21.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 23AD452052; Fri, 6 Dec 2019 16:26:30 +0000 (GMT) Received: from oc3016276355.ibm.com (unknown [9.145.175.63]) by d06av21.portsmouth.uk.ibm.com (Postfix) with ESMTP id BE02D52054; Fri, 6 Dec 2019 16:26:29 +0000 (GMT) From: Pierre Morel To: kvm@vger.kernel.org Cc: linux-s390@vger.kernel.org, frankja@linux.ibm.com, david@redhat.com, thuth@redhat.com, cohuck@redhat.com Subject: [kvm-unit-tests PATCH v3 1/9] s390x: saving regs for interrupts Date: Fri, 6 Dec 2019 17:26:20 +0100 X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1575649588-6127-1-git-send-email-pmorel@linux.ibm.com> References: <1575649588-6127-1-git-send-email-pmorel@linux.ibm.com> X-TM-AS-GCONF: 00 x-cbid: 19120616-0020-0000-0000-0000039509A5 X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 19120616-0021-0000-0000-000021EC3DE7 Message-Id: <1575649588-6127-2-git-send-email-pmorel@linux.ibm.com> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.95,18.0.572 definitions=2019-12-06_05:2019-12-05,2019-12-06 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 priorityscore=1501 clxscore=1015 mlxscore=0 impostorscore=0 bulkscore=0 mlxlogscore=696 suspectscore=1 adultscore=0 phishscore=0 spamscore=0 lowpriorityscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-1910280000 definitions=main-1912060136 Sender: kvm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org If we use multiple source of interrupts, for exemple, using SCLP console to print information while using I/O interrupts, we need to have a re-entrant register saving interruption handling. Instead of saving at a static memory address, let's save the base registers and the floating point registers on the stack. Note that we keep the static register saving to recover from the RESET tests. Signed-off-by: Pierre Morel --- s390x/cstart64.S | 25 +++++++++++++++++++++++-- 1 file changed, 23 insertions(+), 2 deletions(-) diff --git a/s390x/cstart64.S b/s390x/cstart64.S index 86dd4c4..ff05f9b 100644 --- a/s390x/cstart64.S +++ b/s390x/cstart64.S @@ -118,6 +118,25 @@ memsetxc: lmg %r0, %r15, GEN_LC_SW_INT_GRS .endm + .macro SAVE_IRQ_REGS + slgfi %r15, 15 * 8 + stmg %r0, %r14, 0(%r15) + slgfi %r15, 16 * 8 + .irp i, 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15 + std \i, \i * 8(%r15) + .endr + lgr %r2, %r15 + .endm + + .macro RESTORE_IRQ_REGS + .irp i, 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15 + ld \i, \i * 8(%r15) + .endr + algfi %r15, 16 * 8 + lmg %r0, %r14, 0(%r15) + algfi %r15, 15 * 8 + .endm + .section .text /* * load_reset calling convention: @@ -154,6 +173,8 @@ diag308_load_reset: lpswe GEN_LC_SW_INT_PSW 1: br %r14 + + .globl smp_cpu_setup_state smp_cpu_setup_state: xgr %r1, %r1 @@ -180,9 +201,9 @@ mcck_int: lpswe GEN_LC_MCCK_OLD_PSW io_int: - SAVE_REGS + SAVE_IRQ_REGS brasl %r14, handle_io_int - RESTORE_REGS + RESTORE_IRQ_REGS lpswe GEN_LC_IO_OLD_PSW svc_int: