From patchwork Fri Apr 24 10:45:43 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pierre Morel X-Patchwork-Id: 11507509 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 2485D1575 for ; Fri, 24 Apr 2020 10:46:01 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 15FA32064A for ; Fri, 24 Apr 2020 10:46:01 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726746AbgDXKqA (ORCPT ); Fri, 24 Apr 2020 06:46:00 -0400 Received: from mx0b-001b2d01.pphosted.com ([148.163.158.5]:10104 "EHLO mx0a-001b2d01.pphosted.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1726489AbgDXKqA (ORCPT ); Fri, 24 Apr 2020 06:46:00 -0400 Received: from pps.filterd (m0098417.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id 03OAXdCF038456; Fri, 24 Apr 2020 06:45:59 -0400 Received: from pps.reinject (localhost [127.0.0.1]) by mx0a-001b2d01.pphosted.com with ESMTP id 30kpq45x80-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 24 Apr 2020 06:45:58 -0400 Received: from m0098417.ppops.net (m0098417.ppops.net [127.0.0.1]) by pps.reinject (8.16.0.36/8.16.0.36) with SMTP id 03OAZP4c046995; Fri, 24 Apr 2020 06:45:58 -0400 Received: from ppma03ams.nl.ibm.com (62.31.33a9.ip4.static.sl-reverse.com [169.51.49.98]) by mx0a-001b2d01.pphosted.com with ESMTP id 30kpq45x78-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 24 Apr 2020 06:45:58 -0400 Received: from pps.filterd (ppma03ams.nl.ibm.com [127.0.0.1]) by ppma03ams.nl.ibm.com (8.16.0.27/8.16.0.27) with SMTP id 03OAjTqe022195; Fri, 24 Apr 2020 10:45:56 GMT Received: from b06cxnps4075.portsmouth.uk.ibm.com (d06relay12.portsmouth.uk.ibm.com [9.149.109.197]) by ppma03ams.nl.ibm.com with ESMTP id 30fs65921v-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 24 Apr 2020 10:45:56 +0000 Received: from d06av23.portsmouth.uk.ibm.com (d06av23.portsmouth.uk.ibm.com [9.149.105.59]) by b06cxnps4075.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 03OAjsrW1179926 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Fri, 24 Apr 2020 10:45:54 GMT Received: from d06av23.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 9764FA4040; Fri, 24 Apr 2020 10:45:54 +0000 (GMT) Received: from d06av23.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 4560DA4053; Fri, 24 Apr 2020 10:45:54 +0000 (GMT) Received: from oc3016276355.ibm.com (unknown [9.145.79.138]) by d06av23.portsmouth.uk.ibm.com (Postfix) with ESMTP; Fri, 24 Apr 2020 10:45:54 +0000 (GMT) From: Pierre Morel To: kvm@vger.kernel.org Cc: linux-s390@vger.kernel.org, frankja@linux.ibm.com, david@redhat.com, thuth@redhat.com, cohuck@redhat.com Subject: [kvm-unit-tests PATCH v6 01/10] s390x: saving regs for interrupts Date: Fri, 24 Apr 2020 12:45:43 +0200 Message-Id: <1587725152-25569-2-git-send-email-pmorel@linux.ibm.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1587725152-25569-1-git-send-email-pmorel@linux.ibm.com> References: <1587725152-25569-1-git-send-email-pmorel@linux.ibm.com> X-TM-AS-GCONF: 00 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.138,18.0.676 definitions=2020-04-24_04:2020-04-23,2020-04-24 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 malwarescore=0 adultscore=0 clxscore=1015 suspectscore=1 mlxscore=0 priorityscore=1501 phishscore=0 spamscore=0 impostorscore=0 mlxlogscore=950 lowpriorityscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2003020000 definitions=main-2004240082 Sender: kvm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org If we use multiple source of interrupts, for example, using SCLP console to print information while using I/O interrupts, we need to have a re-entrant register saving interruption handling. Instead of saving at a static memory address, let's save the base registers and the floating point registers on the stack. Note that we keep the static register saving to recover from the RESET tests. Signed-off-by: Pierre Morel --- s390x/cstart64.S | 34 ++++++++++++++++++++++++++++++++-- 1 file changed, 32 insertions(+), 2 deletions(-) diff --git a/s390x/cstart64.S b/s390x/cstart64.S index 9af6bb3..ba2e67c 100644 --- a/s390x/cstart64.S +++ b/s390x/cstart64.S @@ -118,6 +118,36 @@ memsetxc: lmg %r0, %r15, GEN_LC_SW_INT_GRS .endm +/* Save registers on the stack (r15), so we can have stacked interrupts. */ + .macro SAVE_IRQ_REGS + /* Allocate a stack frame for 15 integer registers */ + slgfi %r15, 15 * 8 + /* Store all registers from r0 to r14 on the stack */ + stmg %r0, %r14, 0(%r15) + /* Allocate a stack frame for 16 floating point registers */ + /* The size of a FP register is the size of an integer */ + slgfi %r15, 16 * 8 + /* Save fp register on stack: offset to SP is multiple of reg number */ + .irp i, 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15 + std \i, \i * 8(%r15) + .endr + .endm + +/* Restore the register in reverse order */ + .macro RESTORE_IRQ_REGS + /* Restore fp register from stack: SP still where it was left */ + /* and offset to SP is a multile of reg number */ + .irp i, 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15 + ld \i, \i * 8(%r15) + .endr + /* Now it is done, rewind the stack pointer by 16 integers */ + algfi %r15, 16 * 8 + /* Load the registers from stack */ + lmg %r0, %r14, 0(%r15) + /* Rewind the stack by 15 integers */ + algfi %r15, 15 * 8 + .endm + .section .text /* * load_reset calling convention: @@ -182,9 +212,9 @@ mcck_int: lpswe GEN_LC_MCCK_OLD_PSW io_int: - SAVE_REGS + SAVE_IRQ_REGS brasl %r14, handle_io_int - RESTORE_REGS + RESTORE_IRQ_REGS lpswe GEN_LC_IO_OLD_PSW svc_int: