From patchwork Mon Jun 15 09:31:51 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pierre Morel X-Patchwork-Id: 11604461 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 4E88190 for ; Mon, 15 Jun 2020 09:32:39 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 40D2920707 for ; Mon, 15 Jun 2020 09:32:39 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729301AbgFOJce (ORCPT ); Mon, 15 Jun 2020 05:32:34 -0400 Received: from mx0a-001b2d01.pphosted.com ([148.163.156.1]:45326 "EHLO mx0a-001b2d01.pphosted.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729034AbgFOJcO (ORCPT ); Mon, 15 Jun 2020 05:32:14 -0400 Received: from pps.filterd (m0098404.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id 05F86CFY167960; Mon, 15 Jun 2020 05:32:13 -0400 Received: from pps.reinject (localhost [127.0.0.1]) by mx0a-001b2d01.pphosted.com with ESMTP id 31mut8uxnr-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 15 Jun 2020 05:32:13 -0400 Received: from m0098404.ppops.net (m0098404.ppops.net [127.0.0.1]) by pps.reinject (8.16.0.36/8.16.0.36) with SMTP id 05F9WBXe168752; Mon, 15 Jun 2020 05:32:11 -0400 Received: from ppma04ams.nl.ibm.com (63.31.33a9.ip4.static.sl-reverse.com [169.51.49.99]) by mx0a-001b2d01.pphosted.com with ESMTP id 31mut8uxmv-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 15 Jun 2020 05:32:11 -0400 Received: from pps.filterd (ppma04ams.nl.ibm.com [127.0.0.1]) by ppma04ams.nl.ibm.com (8.16.0.42/8.16.0.42) with SMTP id 05F9M1DR013399; Mon, 15 Jun 2020 09:32:07 GMT Received: from b06cxnps3075.portsmouth.uk.ibm.com (d06relay10.portsmouth.uk.ibm.com [9.149.109.195]) by ppma04ams.nl.ibm.com with ESMTP id 31mpe7u8w6-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 15 Jun 2020 09:32:06 +0000 Received: from d06av21.portsmouth.uk.ibm.com (d06av21.portsmouth.uk.ibm.com [9.149.105.232]) by b06cxnps3075.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 05F9W4F528508278 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Mon, 15 Jun 2020 09:32:04 GMT Received: from d06av21.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id EB39752052; Mon, 15 Jun 2020 09:32:03 +0000 (GMT) Received: from oc3016276355.ibm.com (unknown [9.145.1.141]) by d06av21.portsmouth.uk.ibm.com (Postfix) with ESMTP id 8AA3952079; Mon, 15 Jun 2020 09:32:03 +0000 (GMT) From: Pierre Morel To: kvm@vger.kernel.org Cc: linux-s390@vger.kernel.org, frankja@linux.ibm.com, david@redhat.com, thuth@redhat.com, cohuck@redhat.com Subject: [kvm-unit-tests PATCH v9 02/12] s390x: Move control register bit definitions and add AFP to them Date: Mon, 15 Jun 2020 11:31:51 +0200 Message-Id: <1592213521-19390-3-git-send-email-pmorel@linux.ibm.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1592213521-19390-1-git-send-email-pmorel@linux.ibm.com> References: <1592213521-19390-1-git-send-email-pmorel@linux.ibm.com> X-TM-AS-GCONF: 00 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.216,18.0.687 definitions=2020-06-15_01:2020-06-15,2020-06-15 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxscore=0 cotscore=-2147483648 lowpriorityscore=0 malwarescore=0 bulkscore=0 adultscore=0 spamscore=0 mlxlogscore=999 phishscore=0 clxscore=1015 suspectscore=1 priorityscore=1501 impostorscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2004280000 definitions=main-2006150066 Sender: kvm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org While adding the definition for the AFP-Register control bit, move all existing definitions for CR0 out of the C zone to the assmbler zone to keep the definitions concerning CR0 together. Signed-off-by: Pierre Morel Reviewed-by: David Hildenbrand Reviewed-by: Janosch Frank Reviewed-by: Cornelia Huck Acked-by: Thomas Huth --- lib/s390x/asm/arch_def.h | 11 ++++++----- s390x/cstart64.S | 2 +- 2 files changed, 7 insertions(+), 6 deletions(-) diff --git a/lib/s390x/asm/arch_def.h b/lib/s390x/asm/arch_def.h index b5d7aca..fa71653 100644 --- a/lib/s390x/asm/arch_def.h +++ b/lib/s390x/asm/arch_def.h @@ -19,17 +19,18 @@ #define PSW_MASK_ON_EXCEPTION (PSW_MASK_EA | PSW_MASK_BA) +#define CR0_EXTM_SCLP 0x0000000000000200UL +#define CR0_EXTM_EXTC 0x0000000000002000UL +#define CR0_EXTM_EMGC 0x0000000000004000UL +#define CR0_EXTM_MASK 0x0000000000006200UL +#define CR0_AFP_REG_CRTL 0x0000000000040000UL + #ifndef __ASSEMBLER__ struct psw { uint64_t mask; uint64_t addr; }; -#define CR0_EXTM_SCLP 0x0000000000000200UL -#define CR0_EXTM_EXTC 0x0000000000002000UL -#define CR0_EXTM_EMGC 0x0000000000004000UL -#define CR0_EXTM_MASK 0x0000000000006200UL - struct lowcore { uint8_t pad_0x0000[0x0080 - 0x0000]; /* 0x0000 */ uint32_t ext_int_param; /* 0x0080 */ diff --git a/s390x/cstart64.S b/s390x/cstart64.S index d386f35..e7327ea 100644 --- a/s390x/cstart64.S +++ b/s390x/cstart64.S @@ -214,4 +214,4 @@ svc_int_psw: .quad PSW_MASK_ON_EXCEPTION, svc_int initial_cr0: /* enable AFP-register control, so FP regs (+BFP instr) can be used */ - .quad 0x0000000000040000 + .quad CR0_AFP_REG_CRTL