| Message ID | 1628235745-26566-14-git-send-email-weijiang.yang@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Introduce Architectural LBR for vPMU | expand |
On 6/8/2021 3:42 pm, Yang Weijiang wrote: > Per ISA spec, need to clear the bit before inject #DB. Please paste the SDM statement accurately so that the reviewers can verify that the code is consistent with the documentation. > > Signed-off-by: Yang Weijiang <weijiang.yang@intel.com> > --- > arch/x86/kvm/vmx/vmx.c | 21 +++++++++++++++++++++ > 1 file changed, 21 insertions(+) > > diff --git a/arch/x86/kvm/vmx/vmx.c b/arch/x86/kvm/vmx/vmx.c > index 70314cd93340..31b9c06c9b3b 100644 > --- a/arch/x86/kvm/vmx/vmx.c > +++ b/arch/x86/kvm/vmx/vmx.c > @@ -1601,6 +1601,21 @@ static void vmx_clear_hlt(struct kvm_vcpu *vcpu) > vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE); > } > > +static void flip_arch_lbr_ctl(struct kvm_vcpu *vcpu, bool on) > +{ > + if (vcpu_to_pmu(vcpu)->event_count > 0 && Ugh, this check seems ridiculous/funny to me. > + kvm_cpu_cap_has(X86_FEATURE_ARCH_LBR)) { > + u64 lbr_ctl = vmcs_read64(GUEST_IA32_LBR_CTL); > + > + if (on) > + lbr_ctl |= 1ULL; > + else > + lbr_ctl &= ~1ULL; > + > + vmcs_write64(GUEST_IA32_LBR_CTL, lbr_ctl); > + } > +} ...
On Mon, Aug 09, 2021 at 01:08:32PM +0800, Like Xu wrote: > On 6/8/2021 3:42 pm, Yang Weijiang wrote: > >Per ISA spec, need to clear the bit before inject #DB. > > Please paste the SDM statement accurately so that the reviewers > can verify that the code is consistent with the documentation. > Thanks Like! Sure, will add the description in commit message. > > > >Signed-off-by: Yang Weijiang <weijiang.yang@intel.com> > >--- > > arch/x86/kvm/vmx/vmx.c | 21 +++++++++++++++++++++ > > 1 file changed, 21 insertions(+) > > > >diff --git a/arch/x86/kvm/vmx/vmx.c b/arch/x86/kvm/vmx/vmx.c > >index 70314cd93340..31b9c06c9b3b 100644 > >--- a/arch/x86/kvm/vmx/vmx.c > >+++ b/arch/x86/kvm/vmx/vmx.c > >@@ -1601,6 +1601,21 @@ static void vmx_clear_hlt(struct kvm_vcpu *vcpu) > > vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE); > > } > >+static void flip_arch_lbr_ctl(struct kvm_vcpu *vcpu, bool on) > >+{ > >+ if (vcpu_to_pmu(vcpu)->event_count > 0 && > > Ugh, this check seems ridiculous/funny to me. Do you expect aditional bit-check for INTEL_PMC_IDX_FIXED_VLBR in pmu->pmc_in_use? > > >+ kvm_cpu_cap_has(X86_FEATURE_ARCH_LBR)) { > >+ u64 lbr_ctl = vmcs_read64(GUEST_IA32_LBR_CTL); > >+ > >+ if (on) > >+ lbr_ctl |= 1ULL; > >+ else > >+ lbr_ctl &= ~1ULL; > >+ > >+ vmcs_write64(GUEST_IA32_LBR_CTL, lbr_ctl); > >+ } > >+} > > ...
diff --git a/arch/x86/kvm/vmx/vmx.c b/arch/x86/kvm/vmx/vmx.c index 70314cd93340..31b9c06c9b3b 100644 --- a/arch/x86/kvm/vmx/vmx.c +++ b/arch/x86/kvm/vmx/vmx.c @@ -1601,6 +1601,21 @@ static void vmx_clear_hlt(struct kvm_vcpu *vcpu) vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE); } +static void flip_arch_lbr_ctl(struct kvm_vcpu *vcpu, bool on) +{ + if (vcpu_to_pmu(vcpu)->event_count > 0 && + kvm_cpu_cap_has(X86_FEATURE_ARCH_LBR)) { + u64 lbr_ctl = vmcs_read64(GUEST_IA32_LBR_CTL); + + if (on) + lbr_ctl |= 1ULL; + else + lbr_ctl &= ~1ULL; + + vmcs_write64(GUEST_IA32_LBR_CTL, lbr_ctl); + } +} + static void vmx_queue_exception(struct kvm_vcpu *vcpu) { struct vcpu_vmx *vmx = to_vmx(vcpu); @@ -1636,6 +1651,9 @@ static void vmx_queue_exception(struct kvm_vcpu *vcpu) vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info); vmx_clear_hlt(vcpu); + + if (nr == DB_VECTOR) + flip_arch_lbr_ctl(vcpu, false); } static void vmx_setup_uret_msr(struct vcpu_vmx *vmx, unsigned int msr, @@ -4572,6 +4590,9 @@ static void vmx_inject_nmi(struct kvm_vcpu *vcpu) INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR); vmx_clear_hlt(vcpu); + + if (vcpu->arch.exception.nr == DB_VECTOR) + flip_arch_lbr_ctl(vcpu, false); } bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
Per ISA spec, need to clear the bit before inject #DB. Signed-off-by: Yang Weijiang <weijiang.yang@intel.com> --- arch/x86/kvm/vmx/vmx.c | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+)