| Message ID | 1629791777-16430-16-git-send-email-weijiang.yang@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Introduce Architectural LBR for vPMU | expand |
s/Advise/Advertise On Tue, Aug 24, 2021, Yang Weijiang wrote: > Add Arch LBR feature bit in CPU cap-mask to expose the feature. > Only max LBR depth is supported for guest, and it's consistent > with host Arch LBR settings. > > Co-developed-by: Like Xu <like.xu@linux.intel.com> > Signed-off-by: Like Xu <like.xu@linux.intel.com> > Signed-off-by: Yang Weijiang <weijiang.yang@intel.com> > --- > arch/x86/kvm/cpuid.c | 33 ++++++++++++++++++++++++++++++++- > 1 file changed, 32 insertions(+), 1 deletion(-) > > diff --git a/arch/x86/kvm/cpuid.c b/arch/x86/kvm/cpuid.c > index 03025eea1524..d98ebefd5d72 100644 > --- a/arch/x86/kvm/cpuid.c > +++ b/arch/x86/kvm/cpuid.c > @@ -88,6 +88,16 @@ static int kvm_check_cpuid(struct kvm_cpuid_entry2 *entries, int nent) > if (vaddr_bits != 48 && vaddr_bits != 57 && vaddr_bits != 0) > return -EINVAL; > } > + best = cpuid_entry2_find(entries, nent, 0x1c, 0); > + if (best) { > + unsigned int eax, ebx, ecx, edx; > + > + /* Reject user-space CPUID if depth is different from host's.*/ Why disallow this? I don't see why it would be illegal for userspace to specify fewer LBRs, and KVM should darn well verify that any MSRs it's exposing to the guest actually exist. > + cpuid_count(0x1c, 0, &eax, &ebx, &ecx, &edx); > + > + if ((best->eax & 0xff) != BIT(fls(eax & 0xff) - 1)) > + return -EINVAL; > + } > > return 0; > }
On Fri, Oct 15, 2021 at 12:01:22AM +0000, Sean Christopherson wrote: > s/Advise/Advertise > > On Tue, Aug 24, 2021, Yang Weijiang wrote: > > Add Arch LBR feature bit in CPU cap-mask to expose the feature. > > Only max LBR depth is supported for guest, and it's consistent > > with host Arch LBR settings. > > > > Co-developed-by: Like Xu <like.xu@linux.intel.com> > > Signed-off-by: Like Xu <like.xu@linux.intel.com> > > Signed-off-by: Yang Weijiang <weijiang.yang@intel.com> > > --- > > arch/x86/kvm/cpuid.c | 33 ++++++++++++++++++++++++++++++++- > > 1 file changed, 32 insertions(+), 1 deletion(-) > > > > diff --git a/arch/x86/kvm/cpuid.c b/arch/x86/kvm/cpuid.c > > index 03025eea1524..d98ebefd5d72 100644 > > --- a/arch/x86/kvm/cpuid.c > > +++ b/arch/x86/kvm/cpuid.c > > @@ -88,6 +88,16 @@ static int kvm_check_cpuid(struct kvm_cpuid_entry2 *entries, int nent) > > if (vaddr_bits != 48 && vaddr_bits != 57 && vaddr_bits != 0) > > return -EINVAL; > > } > > + best = cpuid_entry2_find(entries, nent, 0x1c, 0); > > + if (best) { > > + unsigned int eax, ebx, ecx, edx; > > + > > + /* Reject user-space CPUID if depth is different from host's.*/ > > Why disallow this? I don't see why it would be illegal for userspace to specify > fewer LBRs, and KVM should darn well verify that any MSRs it's exposing to the > guest actually exist. Hi, Sean, Thanks for the comments! The treatment for LBR depth is a bit special, only the host value can be supported now, i.e., 32. If userspace set the value other that 32, would like to notify it as early as possible. Do you want to remove the check here and correct the invalid setting silently when guest is querying CPUID? > > > + cpuid_count(0x1c, 0, &eax, &ebx, &ecx, &edx); > > + > > + if ((best->eax & 0xff) != BIT(fls(eax & 0xff) - 1)) > > + return -EINVAL; > > + } > > > > return 0; > > }
On 15/10/2021 9:28 am, Yang Weijiang wrote: > On Fri, Oct 15, 2021 at 12:01:22AM +0000, Sean Christopherson wrote: >> s/Advise/Advertise >> >> On Tue, Aug 24, 2021, Yang Weijiang wrote: >>> Add Arch LBR feature bit in CPU cap-mask to expose the feature. >>> Only max LBR depth is supported for guest, and it's consistent >>> with host Arch LBR settings. >>> >>> Co-developed-by: Like Xu <like.xu@linux.intel.com> >>> Signed-off-by: Like Xu <like.xu@linux.intel.com> >>> Signed-off-by: Yang Weijiang <weijiang.yang@intel.com> >>> --- >>> arch/x86/kvm/cpuid.c | 33 ++++++++++++++++++++++++++++++++- >>> 1 file changed, 32 insertions(+), 1 deletion(-) >>> >>> diff --git a/arch/x86/kvm/cpuid.c b/arch/x86/kvm/cpuid.c >>> index 03025eea1524..d98ebefd5d72 100644 >>> --- a/arch/x86/kvm/cpuid.c >>> +++ b/arch/x86/kvm/cpuid.c >>> @@ -88,6 +88,16 @@ static int kvm_check_cpuid(struct kvm_cpuid_entry2 *entries, int nent) >>> if (vaddr_bits != 48 && vaddr_bits != 57 && vaddr_bits != 0) >>> return -EINVAL; >>> } >>> + best = cpuid_entry2_find(entries, nent, 0x1c, 0); >>> + if (best) { >>> + unsigned int eax, ebx, ecx, edx; >>> + >>> + /* Reject user-space CPUID if depth is different from host's.*/ >> >> Why disallow this? I don't see why it would be illegal for userspace to specify >> fewer LBRs, The emulation of guest LBR *depends* on the host LBR driver to save/restore LBRs entries (which are pass-through to the guest and store the guest branch instructions rips actually). Currently, the host side does not support the use of different lbr depths on the same host to customize this part of the overhead. The host perf LBR driver assumes that the lbr depths of different tasks on different cpu's are the same and are the maximum value. The KVM LBR implementation may not break it until additional support is applied on the host side. We'd better not let the guest down if the user space specifies fewer or more LBRs, and explicitly rejecting it in the CPUID settings is an option, or just let the error happen. and KVM should darn well verify that any MSRs it's exposing to the >> guest actually exist. > Hi, Sean, > Thanks for the comments! > The treatment for LBR depth is a bit special, only the host value can be > supported now, i.e., 32. If userspace set the value other that 32, would like > to notify it as early as possible. > Do you want to remove the check here and correct the invalid setting silently when > guest is querying CPUID? > >> >>> + cpuid_count(0x1c, 0, &eax, &ebx, &ecx, &edx); >>> + >>> + if ((best->eax & 0xff) != BIT(fls(eax & 0xff) - 1)) >>> + return -EINVAL; >>> + } >>> >>> return 0; >>> }
On Fri, Oct 15, 2021, Like Xu wrote: > On 15/10/2021 9:28 am, Yang Weijiang wrote: > > On Fri, Oct 15, 2021 at 12:01:22AM +0000, Sean Christopherson wrote: > > > s/Advise/Advertise > > > > > > On Tue, Aug 24, 2021, Yang Weijiang wrote: > > > > Add Arch LBR feature bit in CPU cap-mask to expose the feature. > > > > Only max LBR depth is supported for guest, and it's consistent > > > > with host Arch LBR settings. > > > > > > > > Co-developed-by: Like Xu <like.xu@linux.intel.com> > > > > Signed-off-by: Like Xu <like.xu@linux.intel.com> > > > > Signed-off-by: Yang Weijiang <weijiang.yang@intel.com> > > > > --- > > > > arch/x86/kvm/cpuid.c | 33 ++++++++++++++++++++++++++++++++- > > > > 1 file changed, 32 insertions(+), 1 deletion(-) > > > > > > > > diff --git a/arch/x86/kvm/cpuid.c b/arch/x86/kvm/cpuid.c > > > > index 03025eea1524..d98ebefd5d72 100644 > > > > --- a/arch/x86/kvm/cpuid.c > > > > +++ b/arch/x86/kvm/cpuid.c > > > > @@ -88,6 +88,16 @@ static int kvm_check_cpuid(struct kvm_cpuid_entry2 *entries, int nent) > > > > if (vaddr_bits != 48 && vaddr_bits != 57 && vaddr_bits != 0) > > > > return -EINVAL; > > > > } > > > > + best = cpuid_entry2_find(entries, nent, 0x1c, 0); > > > > + if (best) { > > > > + unsigned int eax, ebx, ecx, edx; > > > > + > > > > + /* Reject user-space CPUID if depth is different from host's.*/ > > > > > > Why disallow this? I don't see why it would be illegal for userspace to specify > > > fewer LBRs, > > The emulation of guest LBR *depends* on the host LBR driver to save/restore > LBRs entries (which are pass-through to the guest and store the guest branch > instructions rips actually). > > Currently, the host side does not support the use of different lbr depths on > the same host to customize this part of the overhead. The host perf LBR > driver assumes that the lbr depths of different tasks on different cpu's are > the same and are the maximum value. Yes, I assumed as much, but saving/restoring MSRs that the guest does not have access to is not a functional issue, just a waste of cycles.
diff --git a/arch/x86/kvm/cpuid.c b/arch/x86/kvm/cpuid.c index 03025eea1524..d98ebefd5d72 100644 --- a/arch/x86/kvm/cpuid.c +++ b/arch/x86/kvm/cpuid.c @@ -88,6 +88,16 @@ static int kvm_check_cpuid(struct kvm_cpuid_entry2 *entries, int nent) if (vaddr_bits != 48 && vaddr_bits != 57 && vaddr_bits != 0) return -EINVAL; } + best = cpuid_entry2_find(entries, nent, 0x1c, 0); + if (best) { + unsigned int eax, ebx, ecx, edx; + + /* Reject user-space CPUID if depth is different from host's.*/ + cpuid_count(0x1c, 0, &eax, &ebx, &ecx, &edx); + + if ((best->eax & 0xff) != BIT(fls(eax & 0xff) - 1)) + return -EINVAL; + } return 0; } @@ -490,7 +500,7 @@ void kvm_set_cpu_caps(void) F(AVX512_4VNNIW) | F(AVX512_4FMAPS) | F(SPEC_CTRL) | F(SPEC_CTRL_SSBD) | F(ARCH_CAPABILITIES) | F(INTEL_STIBP) | F(MD_CLEAR) | F(AVX512_VP2INTERSECT) | F(FSRM) | - F(SERIALIZE) | F(TSXLDTRK) | F(AVX512_FP16) + F(SERIALIZE) | F(TSXLDTRK) | F(AVX512_FP16) | F(ARCH_LBR) ); /* TSC_ADJUST and ARCH_CAPABILITIES are emulated in software. */ @@ -903,6 +913,27 @@ static inline int __do_cpuid_func(struct kvm_cpuid_array *array, u32 function) goto out; } break; + /* Architectural LBR */ + case 0x1c: { + u32 lbr_depth_mask = entry->eax & 0xff; + + if (!lbr_depth_mask || + !kvm_cpu_cap_has(X86_FEATURE_ARCH_LBR)) { + entry->eax = entry->ebx = entry->ecx = entry->edx = 0; + break; + } + /* + * KVM only exposes the maximum supported depth, which is the + * fixed value used on the host side. + * KVM doesn't allow VMM userspace to adjust LBR depth because + * guest LBR emulation depends on the configuration of host LBR + * driver. + */ + lbr_depth_mask = BIT((fls(lbr_depth_mask) - 1)); + entry->eax &= ~0xff; + entry->eax |= lbr_depth_mask; + break; + } case KVM_CPUID_SIGNATURE: { static const char signature[12] = "KVMKVMKVM\0\0"; const u32 *sigptr = (const u32 *)signature;