From patchwork Mon Nov 16 18:26:48 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Isaku Yamahata X-Patchwork-Id: 11910339 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id E0A2FC61DD8 for ; Mon, 16 Nov 2020 18:28:55 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id A0E5C2231B for ; Mon, 16 Nov 2020 18:28:55 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2388423AbgKPS2s (ORCPT ); Mon, 16 Nov 2020 13:28:48 -0500 Received: from mga02.intel.com ([134.134.136.20]:48458 "EHLO mga02.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2388337AbgKPS2X (ORCPT ); Mon, 16 Nov 2020 13:28:23 -0500 IronPort-SDR: jQlx1HG65Jyy1JiKjz5FLH/EeFSoCpvB8MgDvjwXE+Vl5UPGGkGY/KYO9NHzODsS+Pdt/1xUVb zu4lmfBKtu6g== X-IronPort-AV: E=McAfee;i="6000,8403,9807"; a="157819213" X-IronPort-AV: E=Sophos;i="5.77,483,1596524400"; d="scan'208";a="157819213" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga001.jf.intel.com ([10.7.209.18]) by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Nov 2020 10:28:22 -0800 IronPort-SDR: ugxbilTI9eOuuteaQH2t/r+tGicD2+WLH7F8pD2PSYyMubmdgyHpeMa54D5RFrsg6000ZjO8gz NDdX2Huf4b/w== X-IronPort-AV: E=Sophos;i="5.77,483,1596524400"; d="scan'208";a="400528381" Received: from ls.sc.intel.com (HELO localhost) ([143.183.96.54]) by orsmga001-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Nov 2020 10:28:22 -0800 From: isaku.yamahata@intel.com To: Thomas Gleixner , Ingo Molnar , Borislav Petkov , "H . Peter Anvin" , Paolo Bonzini , Vitaly Kuznetsov , Wanpeng Li , Jim Mattson , Joerg Roedel , x86@kernel.org, linux-kernel@vger.kernel.org, kvm@vger.kernel.org Cc: isaku.yamahata@intel.com, isaku.yamahata@gmail.com, Kai Huang Subject: [RFC PATCH 63/67] cpu/hotplug: Document that TDX also depends on booting CPUs once Date: Mon, 16 Nov 2020 10:26:48 -0800 Message-Id: <1d588f512e13b0342e6e76aabb2263440bdde8f8.1605232743.git.isaku.yamahata@intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: References: In-Reply-To: References: Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org From: Kai Huang Add a comment to explain that TDX also depends on booting logical CPUs at least once. TDSYSINITLP must be run on all CPUs, even software disabled CPUs in the -nosmt case. Fortunately, current SMT handling for #MC already supports booting all CPUs once; the to-be-disabled sibling is booted once (and later put into deep C-state to honor SMT=off) to allow the init code to set CR4.MCE and avoid an unwanted shutdown on a broadcasted MCE. Signed-off-by: Kai Huang --- kernel/cpu.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/kernel/cpu.c b/kernel/cpu.c index 6ff2578ecf17..17a8d7db99b2 100644 --- a/kernel/cpu.c +++ b/kernel/cpu.c @@ -435,6 +435,10 @@ static inline bool cpu_smt_allowed(unsigned int cpu) * that the init code can get a chance to set CR4.MCE on each * CPU. Otherwise, a broadcasted MCE observing CR4.MCE=0b on any * core will shutdown the machine. + * + * Intel TDX also requires running TDSYSINITLP on all logical CPUs + * during boot, booting all CPUs once allows TDX to play nice with + * 'nosmt'. */ return !cpumask_test_cpu(cpu, &cpus_booted_once_mask); }