| Message ID | 1df5271baa641d9d189edb86f9ee0921ea3a83e0.1646422845.git.isaku.yamahata@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | KVM TDX basic feature support | expand |
On Fri, Mar 4, 2022 at 12:23 PM <isaku.yamahata@intel.com> wrote: > > From: Isaku Yamahata <isaku.yamahata@intel.com> > > On EPT violation, call a common function, __vmx_handle_ept_violation() to > trigger x86 MMU code. On EPT misconfiguration, exit to ring 3 with > KVM_EXIT_UNKNOWN. because EPT misconfiguration can't happen as MMIO is > trigged by TDG.VP.VMCALL. No point to set a misconfiguration value for the > fast path. > > Signed-off-by: Isaku Yamahata <isaku.yamahata@intel.com> > --- > arch/x86/kvm/vmx/tdx.c | 40 ++++++++++++++++++++++++++++++++++++++-- > 1 file changed, 38 insertions(+), 2 deletions(-) > > diff --git a/arch/x86/kvm/vmx/tdx.c b/arch/x86/kvm/vmx/tdx.c > index 6fbe89bcfe1e..2c35dcad077e 100644 > --- a/arch/x86/kvm/vmx/tdx.c > +++ b/arch/x86/kvm/vmx/tdx.c > @@ -1081,6 +1081,40 @@ void tdx_deliver_interrupt(struct kvm_lapic *apic, int delivery_mode, > __vmx_deliver_posted_interrupt(vcpu, &tdx->pi_desc, vector); > } > > +#define TDX_SEPT_PFERR (PFERR_WRITE_MASK | PFERR_USER_MASK) TDX_SEPT_PFERR is defined using PFERR_.* bitmask but __vmx_handle_ept_violation is accepting an EPT_VIOLATION_.* bitmask. so (PFERR_WRITE_MASK | PFERR_USER_MASK) will get interpreted as (EPT_VIOLATION_ACC_WRITE | EPT_VIOLATION_ACC_INSTR) which will get translated to (PFERR_WRITE_MASK | PFERR_FETCH_MASK). Was that the intention of this code? > + > +static int tdx_handle_ept_violation(struct kvm_vcpu *vcpu) > +{ > + unsigned long exit_qual; > + > + if (kvm_is_private_gpa(vcpu->kvm, tdexit_gpa(vcpu))) > + exit_qual = TDX_SEPT_PFERR; > + else { > + exit_qual = tdexit_exit_qual(vcpu); > + if (exit_qual & EPT_VIOLATION_ACC_INSTR) { > + pr_warn("kvm: TDX instr fetch to shared GPA = 0x%lx @ RIP = 0x%lx\n", > + tdexit_gpa(vcpu), kvm_rip_read(vcpu)); > + vcpu->run->exit_reason = KVM_EXIT_EXCEPTION; > + vcpu->run->ex.exception = PF_VECTOR; > + vcpu->run->ex.error_code = exit_qual; > + return 0; > + } > + } > + > + trace_kvm_page_fault(tdexit_gpa(vcpu), exit_qual); > + return __vmx_handle_ept_violation(vcpu, tdexit_gpa(vcpu), exit_qual); > +} > + > +static int tdx_handle_ept_misconfig(struct kvm_vcpu *vcpu) > +{ > + WARN_ON(1); > + > + vcpu->run->exit_reason = KVM_EXIT_UNKNOWN; > + vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG; > + > + return 0; > +} > + > int tdx_handle_exit(struct kvm_vcpu *vcpu, fastpath_t fastpath) > { > union tdx_exit_reason exit_reason = to_tdx(vcpu)->exit_reason; > @@ -1097,6 +1131,10 @@ int tdx_handle_exit(struct kvm_vcpu *vcpu, fastpath_t fastpath) > WARN_ON_ONCE(fastpath != EXIT_FASTPATH_NONE); > > switch (exit_reason.basic) { > + case EXIT_REASON_EPT_VIOLATION: > + return tdx_handle_ept_violation(vcpu); > + case EXIT_REASON_EPT_MISCONFIG: > + return tdx_handle_ept_misconfig(vcpu); > case EXIT_REASON_OTHER_SMI: > /* > * If reach here, it's not a MSMI. > @@ -1378,8 +1416,6 @@ void tdx_flush_tlb(struct kvm_vcpu *vcpu) > cpu_relax(); > } > > -#define TDX_SEPT_PFERR (PFERR_WRITE_MASK | PFERR_USER_MASK) > - > static int tdx_init_mem_region(struct kvm *kvm, struct kvm_tdx_cmd *cmd) > { > struct kvm_tdx *kvm_tdx = to_kvm_tdx(kvm); > -- > 2.25.1 > Sagi
On 4/7/2022 4:50 AM, Sagi Shahar wrote: > On Fri, Mar 4, 2022 at 12:23 PM <isaku.yamahata@intel.com> wrote: >> >> From: Isaku Yamahata <isaku.yamahata@intel.com> >> >> On EPT violation, call a common function, __vmx_handle_ept_violation() to >> trigger x86 MMU code. On EPT misconfiguration, exit to ring 3 with >> KVM_EXIT_UNKNOWN. because EPT misconfiguration can't happen as MMIO is >> trigged by TDG.VP.VMCALL. No point to set a misconfiguration value for the >> fast path. >> >> Signed-off-by: Isaku Yamahata <isaku.yamahata@intel.com> >> --- >> arch/x86/kvm/vmx/tdx.c | 40 ++++++++++++++++++++++++++++++++++++++-- >> 1 file changed, 38 insertions(+), 2 deletions(-) >> >> diff --git a/arch/x86/kvm/vmx/tdx.c b/arch/x86/kvm/vmx/tdx.c >> index 6fbe89bcfe1e..2c35dcad077e 100644 >> --- a/arch/x86/kvm/vmx/tdx.c >> +++ b/arch/x86/kvm/vmx/tdx.c >> @@ -1081,6 +1081,40 @@ void tdx_deliver_interrupt(struct kvm_lapic *apic, int delivery_mode, >> __vmx_deliver_posted_interrupt(vcpu, &tdx->pi_desc, vector); >> } >> >> +#define TDX_SEPT_PFERR (PFERR_WRITE_MASK | PFERR_USER_MASK) > > TDX_SEPT_PFERR is defined using PFERR_.* bitmask but > __vmx_handle_ept_violation is accepting an EPT_VIOLATION_.* bitmask. > so (PFERR_WRITE_MASK | PFERR_USER_MASK) will get interpreted as > (EPT_VIOLATION_ACC_WRITE | EPT_VIOLATION_ACC_INSTR) which will get > translated to (PFERR_WRITE_MASK | PFERR_FETCH_MASK). Was that the > intention of this code? No. It's a mistake. We have corrected internally you can find corrected code in github repo or see it in next version.
diff --git a/arch/x86/kvm/vmx/tdx.c b/arch/x86/kvm/vmx/tdx.c index 6fbe89bcfe1e..2c35dcad077e 100644 --- a/arch/x86/kvm/vmx/tdx.c +++ b/arch/x86/kvm/vmx/tdx.c @@ -1081,6 +1081,40 @@ void tdx_deliver_interrupt(struct kvm_lapic *apic, int delivery_mode, __vmx_deliver_posted_interrupt(vcpu, &tdx->pi_desc, vector); } +#define TDX_SEPT_PFERR (PFERR_WRITE_MASK | PFERR_USER_MASK) + +static int tdx_handle_ept_violation(struct kvm_vcpu *vcpu) +{ + unsigned long exit_qual; + + if (kvm_is_private_gpa(vcpu->kvm, tdexit_gpa(vcpu))) + exit_qual = TDX_SEPT_PFERR; + else { + exit_qual = tdexit_exit_qual(vcpu); + if (exit_qual & EPT_VIOLATION_ACC_INSTR) { + pr_warn("kvm: TDX instr fetch to shared GPA = 0x%lx @ RIP = 0x%lx\n", + tdexit_gpa(vcpu), kvm_rip_read(vcpu)); + vcpu->run->exit_reason = KVM_EXIT_EXCEPTION; + vcpu->run->ex.exception = PF_VECTOR; + vcpu->run->ex.error_code = exit_qual; + return 0; + } + } + + trace_kvm_page_fault(tdexit_gpa(vcpu), exit_qual); + return __vmx_handle_ept_violation(vcpu, tdexit_gpa(vcpu), exit_qual); +} + +static int tdx_handle_ept_misconfig(struct kvm_vcpu *vcpu) +{ + WARN_ON(1); + + vcpu->run->exit_reason = KVM_EXIT_UNKNOWN; + vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG; + + return 0; +} + int tdx_handle_exit(struct kvm_vcpu *vcpu, fastpath_t fastpath) { union tdx_exit_reason exit_reason = to_tdx(vcpu)->exit_reason; @@ -1097,6 +1131,10 @@ int tdx_handle_exit(struct kvm_vcpu *vcpu, fastpath_t fastpath) WARN_ON_ONCE(fastpath != EXIT_FASTPATH_NONE); switch (exit_reason.basic) { + case EXIT_REASON_EPT_VIOLATION: + return tdx_handle_ept_violation(vcpu); + case EXIT_REASON_EPT_MISCONFIG: + return tdx_handle_ept_misconfig(vcpu); case EXIT_REASON_OTHER_SMI: /* * If reach here, it's not a MSMI. @@ -1378,8 +1416,6 @@ void tdx_flush_tlb(struct kvm_vcpu *vcpu) cpu_relax(); } -#define TDX_SEPT_PFERR (PFERR_WRITE_MASK | PFERR_USER_MASK) - static int tdx_init_mem_region(struct kvm *kvm, struct kvm_tdx_cmd *cmd) { struct kvm_tdx *kvm_tdx = to_kvm_tdx(kvm);