From patchwork Tue Jun 2 15:02:19 2009 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Michael S. Tsirkin" X-Patchwork-Id: 27480 Received: from vger.kernel.org (vger.kernel.org [209.132.176.167]) by demeter.kernel.org (8.14.2/8.14.2) with ESMTP id n52F6xag011479 for ; Tue, 2 Jun 2009 15:07:00 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756315AbZFBPFv (ORCPT ); Tue, 2 Jun 2009 11:05:51 -0400 Received: (majordomo@vger.kernel.org) by vger.kernel.org id S1757211AbZFBPFu (ORCPT ); Tue, 2 Jun 2009 11:05:50 -0400 Received: from mx2.redhat.com ([66.187.237.31]:47694 "EHLO mx2.redhat.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1756788AbZFBPFt (ORCPT ); Tue, 2 Jun 2009 11:05:49 -0400 Received: from int-mx2.corp.redhat.com (int-mx2.corp.redhat.com [172.16.27.26]) by mx2.redhat.com (8.13.8/8.13.8) with ESMTP id n52F3GE4013077; Tue, 2 Jun 2009 11:03:16 -0400 Received: from ns3.rdu.redhat.com (ns3.rdu.redhat.com [10.11.255.199]) by int-mx2.corp.redhat.com (8.13.1/8.13.1) with ESMTP id n52F3EwO011507; Tue, 2 Jun 2009 11:03:15 -0400 Received: from redhat.com (dhcp-0-223.tlv.redhat.com [10.35.0.223]) by ns3.rdu.redhat.com (8.13.8/8.13.8) with ESMTP id n52F3Brw019253; Tue, 2 Jun 2009 11:03:12 -0400 Date: Tue, 2 Jun 2009 18:02:19 +0300 From: "Michael S. Tsirkin" To: Paul Brook , Avi Kivity , qemu-devel@nongnu.org, Carsten Otte , kvm@vger.kernel.org, Rusty Russell , virtualization@lists.linux-foundation.org, Christian Borntraeger , Blue Swirl , Anthony Liguori Subject: [PATCHv2 03/13] qemu: add routines to manage PCI capabilities Message-ID: <20090602150219.GD6554@redhat.com> References: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.18 (2008-05-17) X-Scanned-By: MIMEDefang 2.58 on 172.16.27.26 Sender: kvm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Add routines to manage PCI capability list. First user will be MSI-X. Signed-off-by: Michael S. Tsirkin --- hw/pci.c | 98 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++------ hw/pci.h | 18 +++++++++++- 2 files changed, 106 insertions(+), 10 deletions(-) diff --git a/hw/pci.c b/hw/pci.c index 5dcfb4e..31ba2ed 100644 --- a/hw/pci.c +++ b/hw/pci.c @@ -130,12 +130,13 @@ void pci_device_save(PCIDevice *s, QEMUFile *f) int version = s->cap_present ? 3 : 2; int i; - qemu_put_be32(f, version); /* PCI device version */ + /* PCI device version and capabilities */ + qemu_put_be32(f, version); + if (version >= 3) + qemu_put_be32(f, s->cap_present); qemu_put_buffer(f, s->config, 256); for (i = 0; i < 4; i++) qemu_put_be32(f, s->irq_state[i]); - if (version >= 3) - qemu_put_be32(f, s->cap_present); } int pci_device_load(PCIDevice *s, QEMUFile *f) @@ -146,12 +147,6 @@ int pci_device_load(PCIDevice *s, QEMUFile *f) version_id = qemu_get_be32(f); if (version_id > 3) return -EINVAL; - qemu_get_buffer(f, s->config, 256); - pci_update_mappings(s); - - if (version_id >= 2) - for (i = 0; i < 4; i ++) - s->irq_state[i] = qemu_get_be32(f); if (version_id >= 3) s->cap_present = qemu_get_be32(f); else @@ -160,6 +155,18 @@ int pci_device_load(PCIDevice *s, QEMUFile *f) if (s->cap_present & ~s->cap_supported) return -EINVAL; + qemu_get_buffer(f, s->config, 256); + pci_update_mappings(s); + + if (version_id >= 2) + for (i = 0; i < 4; i ++) + s->irq_state[i] = qemu_get_be32(f); + /* Clear mask and used bits for capabilities. + Must be restored separately, since capabilities can + be placed anywhere in config space. */ + memset(s->used, 0, PCI_CONFIG_SPACE_SIZE); + for (i = PCI_CONFIG_HEADER_SIZE; i < PCI_CONFIG_SPACE_SIZE; ++i) + s->mask[i] = 0xff; return 0; } @@ -870,3 +877,76 @@ PCIDevice *pci_create_simple(PCIBus *bus, int devfn, const char *name) return (PCIDevice *)dev; } + +static int pci_find_space(PCIDevice *pdev, uint8_t size) +{ + int offset = PCI_CONFIG_HEADER_SIZE; + int i; + for (i = PCI_CONFIG_HEADER_SIZE; i < PCI_CONFIG_SPACE_SIZE; ++i) + if (pdev->used[i]) + offset = i + 1; + else if (i - offset + 1 == size) + return offset; + return 0; +} + +static uint8_t pci_find_capability_list(PCIDevice *pdev, uint8_t cap_id, + uint8_t *prev_p) +{ + uint8_t next, prev; + + if (!(pdev->config[PCI_STATUS] & PCI_STATUS_CAP_LIST)) + return 0; + + for (prev = PCI_CAPABILITY_LIST; (next = pdev->config[prev]); + prev = next + PCI_CAP_LIST_NEXT) + if (pdev->config[next + PCI_CAP_LIST_ID] == cap_id) + break; + + *prev_p = prev; + return next; +} + +/* Reserve space and add capability to the linked list in pci config space */ +int pci_add_capability(PCIDevice *pdev, uint8_t cap_id, uint8_t size) +{ + uint8_t offset = pci_find_space(pdev, size); + uint8_t *config = pdev->config + offset; + if (!offset) + return -ENOSPC; + config[PCI_CAP_LIST_ID] = cap_id; + config[PCI_CAP_LIST_NEXT] = pdev->config[PCI_CAPABILITY_LIST]; + pdev->config[PCI_CAPABILITY_LIST] = offset; + pdev->config[PCI_STATUS] |= PCI_STATUS_CAP_LIST; + memset(pdev->used + offset, 0xFF, size); + /* Make capability read-only by default */ + memset(pdev->mask + offset, 0, size); + return offset; +} + +/* Unlink capability from the pci config space. */ +void pci_del_capability(PCIDevice *pdev, uint8_t cap_id, uint8_t size) +{ + uint8_t prev, offset = pci_find_capability_list(pdev, cap_id, &prev); + if (!offset) + return; + pdev->config[prev] = pdev->config[offset + PCI_CAP_LIST_NEXT]; + /* Make capability writeable again */ + memset(pdev->mask + offset, 0xff, size); + memset(pdev->used + offset, 0, size); + + if (!pdev->config[PCI_CAPABILITY_LIST]) + pdev->config[PCI_STATUS] &= ~PCI_STATUS_CAP_LIST; +} + +/* Reserve space for capability at a known offset (to call after load). */ +void pci_reserve_capability(PCIDevice *pdev, uint8_t offset, uint8_t size) +{ + memset(pdev->used + offset, 0xff, size); +} + +uint8_t pci_find_capability(PCIDevice *pdev, uint8_t cap_id) +{ + uint8_t prev; + return pci_find_capability_list(pdev, cap_id, &prev); +} diff --git a/hw/pci.h b/hw/pci.h index 9139504..40137c6 100644 --- a/hw/pci.h +++ b/hw/pci.h @@ -123,6 +123,10 @@ typedef struct PCIIORegion { #define PCI_MIN_GNT 0x3e /* 8 bits */ #define PCI_MAX_LAT 0x3f /* 8 bits */ +/* Capability lists */ +#define PCI_CAP_LIST_ID 0 /* Capability ID */ +#define PCI_CAP_LIST_NEXT 1 /* Next capability in the list */ + #define PCI_REVISION 0x08 /* obsolete, use PCI_REVISION_ID */ #define PCI_SUBVENDOR_ID 0x2c /* obsolete, use PCI_SUBSYSTEM_VENDOR_ID */ #define PCI_SUBDEVICE_ID 0x2e /* obsolete, use PCI_SUBSYSTEM_ID */ @@ -130,7 +134,7 @@ typedef struct PCIIORegion { /* Bits in the PCI Status Register (PCI 2.3 spec) */ #define PCI_STATUS_RESERVED1 0x007 #define PCI_STATUS_INT_STATUS 0x008 -#define PCI_STATUS_CAPABILITIES 0x010 +#define PCI_STATUS_CAP_LIST 0x010 #define PCI_STATUS_66MHZ 0x020 #define PCI_STATUS_RESERVED2 0x040 #define PCI_STATUS_FAST_BACK 0x080 @@ -160,6 +164,9 @@ struct PCIDevice { /* Used to implement R/W bytes */ uint8_t mask[PCI_CONFIG_SPACE_SIZE]; + /* Used to allocate config space for capabilities. */ + uint8_t used[PCI_CONFIG_SPACE_SIZE]; + /* the following fields are read only */ PCIBus *bus; int devfn; @@ -194,6 +201,15 @@ void pci_register_io_region(PCIDevice *pci_dev, int region_num, uint32_t size, int type, PCIMapIORegionFunc *map_func); +int pci_add_capability(PCIDevice *pci_dev, uint8_t cap_id, uint8_t cap_size); + +void pci_del_capability(PCIDevice *pci_dev, uint8_t cap_id, uint8_t cap_size); + +void pci_reserve_capability(PCIDevice *pci_dev, uint8_t offset, uint8_t size); + +uint8_t pci_find_capability(PCIDevice *pci_dev, uint8_t cap_id); + + uint32_t pci_default_read_config(PCIDevice *d, uint32_t address, int len); void pci_default_write_config(PCIDevice *d,