From patchwork Fri Jan 1 18:23:08 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kevin O'Connor X-Patchwork-Id: 70449 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.3/8.14.2) with ESMTP id o01IPfNw023741 for ; Fri, 1 Jan 2010 18:25:41 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751753Ab0AASXM (ORCPT ); Fri, 1 Jan 2010 13:23:12 -0500 Received: (majordomo@vger.kernel.org) by vger.kernel.org id S1751762Ab0AASXM (ORCPT ); Fri, 1 Jan 2010 13:23:12 -0500 Received: from qw-out-2122.google.com ([74.125.92.26]:64308 "EHLO qw-out-2122.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751696Ab0AASXL (ORCPT ); Fri, 1 Jan 2010 13:23:11 -0500 Received: by qw-out-2122.google.com with SMTP id 8so1459469qwh.37 for ; Fri, 01 Jan 2010 10:23:10 -0800 (PST) Received: by 10.229.131.152 with SMTP id x24mr1324293qcs.84.1262370190697; Fri, 01 Jan 2010 10:23:10 -0800 (PST) Received: from localhost (207-172-165-101.s101.tnt1.nywnj.ny.dialup.rcn.com [207.172.165.101]) by mx.google.com with ESMTPS id 23sm14122376qyk.3.2010.01.01.10.23.09 (version=TLSv1/SSLv3 cipher=RC4-MD5); Fri, 01 Jan 2010 10:23:09 -0800 (PST) Date: Fri, 1 Jan 2010 13:23:08 -0500 From: "Kevin O'Connor" To: seabios@seabios.org, kvm@vger.kernel.org Subject: [SeaBIOS] [PATCH] Make MTRR region 0xc0000-0x100000 be cached. Message-ID: <20100101182308.GB10271@morn.localdomain> MIME-Version: 1.0 Content-Disposition: inline User-Agent: Mutt/1.5.19 (2009-01-05) Sender: kvm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org diff --git a/src/mtrr.c b/src/mtrr.c index 7d1df09..ed239c8 100644 --- a/src/mtrr.c +++ b/src/mtrr.c @@ -44,42 +44,42 @@ void mtrr_setup(void) dprintf(3, "init mtrr\n"); - int i, vcnt, fix, wc; - u32 mtrr_cap; - union { - u8 valb[8]; - u64 val; - } u; - - mtrr_cap = rdmsr(MSR_MTRRcap); - vcnt = mtrr_cap & 0xff; - fix = mtrr_cap & 0x100; - wc = mtrr_cap & 0x400; + u32 mtrr_cap = rdmsr(MSR_MTRRcap); + int vcnt = mtrr_cap & 0xff; + int fix = mtrr_cap & 0x100; if (!vcnt || !fix) return; - // Fixed MTRRs + // Disable MTRRs + wrmsr_smp(MSR_MTRRdefType, 0); + + // Set fixed MTRRs + union u64b { + u8 valb[8]; + u64 val; + } u; u.val = 0; - for (i = 0; i < 8; ++i) + int i; + for (i = 0; i < 8; i++) if (RamSize >= 65536 * (i + 1)) u.valb[i] = MTRR_MEMTYPE_WB; wrmsr_smp(MSR_MTRRfix64K_00000, u.val); u.val = 0; - for (i = 0; i < 8; ++i) - if (RamSize >= 65536 * 8 + 16384 * (i + 1)) + for (i = 0; i < 8; i++) + if (RamSize >= 0x80000 + 16384 * (i + 1)) u.valb[i] = MTRR_MEMTYPE_WB; wrmsr_smp(MSR_MTRRfix16K_80000, u.val); - wrmsr_smp(MSR_MTRRfix16K_A0000, 0); - wrmsr_smp(MSR_MTRRfix4K_C0000, 0); - wrmsr_smp(MSR_MTRRfix4K_C8000, 0); - wrmsr_smp(MSR_MTRRfix4K_D0000, 0); - wrmsr_smp(MSR_MTRRfix4K_D8000, 0); - wrmsr_smp(MSR_MTRRfix4K_E0000, 0); - wrmsr_smp(MSR_MTRRfix4K_E8000, 0); - wrmsr_smp(MSR_MTRRfix4K_F0000, 0); - wrmsr_smp(MSR_MTRRfix4K_F8000, 0); + wrmsr_smp(MSR_MTRRfix16K_A0000, 0); // 0xA0000-0xC0000 is uncached + int j; + for (j = 0; j < 8; j++) { + u.val = 0; + for (i = 0; i < 8; i++) + if (RamSize >= 0xC0000 + j * 0x8000 + 4096 * (i + 1)) + u.valb[i] = MTRR_MEMTYPE_WP; + wrmsr_smp(MSR_MTRRfix4K_C0000 + j, u.val); + } - // Variable MTRRs + // Set variable MTRRs int phys_bits = 36; cpuid(0x80000000u, &eax, &ebx, &ecx, &edx); if (eax >= 0x80000008) { @@ -88,6 +88,10 @@ void mtrr_setup(void) phys_bits = eax & 0xff; } u64 phys_mask = ((1ull << phys_bits) - 1); + for (i=0; i