From patchwork Wed Apr 23 18:20:03 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Marcelo Tosatti X-Patchwork-Id: 4043361 Return-Path: X-Original-To: patchwork-kvm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id C55EC9F387 for ; Wed, 23 Apr 2014 18:27:27 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id D9CB0201F7 for ; Wed, 23 Apr 2014 18:27:26 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id AA56920127 for ; Wed, 23 Apr 2014 18:27:25 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1757541AbaDWS1K (ORCPT ); Wed, 23 Apr 2014 14:27:10 -0400 Received: from mx1.redhat.com ([209.132.183.28]:42159 "EHLO mx1.redhat.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754105AbaDWS1I (ORCPT ); Wed, 23 Apr 2014 14:27:08 -0400 Received: from int-mx11.intmail.prod.int.phx2.redhat.com (int-mx11.intmail.prod.int.phx2.redhat.com [10.5.11.24]) by mx1.redhat.com (8.14.4/8.14.4) with ESMTP id s3NIR68w001618 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Wed, 23 Apr 2014 14:27:06 -0400 Received: from amt.cnet (vpn1-4-123.gru2.redhat.com [10.97.4.123]) by int-mx11.intmail.prod.int.phx2.redhat.com (8.14.4/8.14.4) with ESMTP id s3NIR5Zl026368; Wed, 23 Apr 2014 14:27:06 -0400 Received: from amt.cnet (localhost [127.0.0.1]) by amt.cnet (Postfix) with ESMTP id 7E4871003F1; Wed, 23 Apr 2014 15:26:50 -0300 (BRT) Received: (from marcelo@localhost) by amt.cnet (8.14.7/8.14.7/Submit) id s3NIQo8w030039; Wed, 23 Apr 2014 15:26:50 -0300 Message-Id: <20140423182539.311543987@amt.cnet> User-Agent: quilt/0.60-1 Date: Wed, 23 Apr 2014 15:20:03 -0300 From: Marcelo Tosatti To: kvm@vger.kernel.org, qemu-devel@nongnu.org Cc: Paolo Bonzini , Eduardo Habkost , Marcelo Tosatti Subject: [patch 1/2] target-i386: support "invariant tsc" flag References: <20140423182002.441209839@amt.cnet> Content-Disposition: inline; filename=01_qemu-cpuid-invariant.patch X-Scanned-By: MIMEDefang 2.68 on 10.5.11.24 Sender: kvm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org X-Spam-Status: No, score=-7.5 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Expose "Invariant TSC" flag, if KVM is enabled. From Intel documentation: 17.13.1 Invariant TSC The time stamp counter in newer processors may support an enhancement, referred to as invariant TSC. Processor’s support for invariant TSC is indicated by CPUID.80000007H:EDX[8]. The invariant TSC will run at a constant rate in all ACPI P-, C-. and T-states. This is the architectural behavior moving forward. On processors with invariant TSC support, the OS may use the TSC for wall clock timer services (instead of ACPI or HPET timers). TSC reads are much more efficient and do not incur the overhead associated with a ring transition or access to a platform resource. Signed-off-by: Marcelo Tosatti Reviewed-by: Eduardo Habkost --- To unsubscribe from this list: send the line "unsubscribe kvm" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Index: qemu-invariant-tsc/target-i386/cpu.c =================================================================== --- qemu-invariant-tsc.orig/target-i386/cpu.c +++ qemu-invariant-tsc/target-i386/cpu.c @@ -262,6 +262,17 @@ static const char *cpuid_7_0_ebx_feature NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, }; +static const char *cpuid_apm_edx_feature_name[] = { + NULL, NULL, NULL, NULL, + NULL, NULL, NULL, NULL, + "invtsc", NULL, NULL, NULL, + NULL, NULL, NULL, NULL, + NULL, NULL, NULL, NULL, + NULL, NULL, NULL, NULL, + NULL, NULL, NULL, NULL, + NULL, NULL, NULL, NULL, +}; + typedef struct FeatureWordInfo { const char **feat_names; uint32_t cpuid_eax; /* Input EAX for CPUID */ @@ -305,6 +316,11 @@ static FeatureWordInfo feature_word_info .cpuid_needs_ecx = true, .cpuid_ecx = 0, .cpuid_reg = R_EBX, }, + [FEAT_8000_0007_EDX] = { + .feat_names = cpuid_apm_edx_feature_name, + .cpuid_eax = 0x80000007, + .cpuid_reg = R_EDX, + }, }; typedef struct X86RegisterInfo32 { @@ -580,6 +596,7 @@ struct X86CPUDefinition { CPUID_7_0_EBX_FSGSBASE, CPUID_7_0_EBX_HLE, CPUID_7_0_EBX_AVX2, CPUID_7_0_EBX_ERMS, CPUID_7_0_EBX_INVPCID, CPUID_7_0_EBX_RTM, CPUID_7_0_EBX_RDSEED */ +#define TCG_APM_FEATURES 0 static X86CPUDefinition builtin_x86_defs[] = { { @@ -1740,6 +1757,7 @@ static void x86_cpu_parse_featurestr(CPU env->features[FEAT_1_ECX] |= plus_features[FEAT_1_ECX]; env->features[FEAT_8000_0001_EDX] |= plus_features[FEAT_8000_0001_EDX]; env->features[FEAT_8000_0001_ECX] |= plus_features[FEAT_8000_0001_ECX]; + env->features[FEAT_8000_0007_EDX] |= plus_features[FEAT_8000_0007_EDX]; env->features[FEAT_C000_0001_EDX] |= plus_features[FEAT_C000_0001_EDX]; env->features[FEAT_KVM] |= plus_features[FEAT_KVM]; env->features[FEAT_SVM] |= plus_features[FEAT_SVM]; @@ -1748,6 +1766,7 @@ static void x86_cpu_parse_featurestr(CPU env->features[FEAT_1_ECX] &= ~minus_features[FEAT_1_ECX]; env->features[FEAT_8000_0001_EDX] &= ~minus_features[FEAT_8000_0001_EDX]; env->features[FEAT_8000_0001_ECX] &= ~minus_features[FEAT_8000_0001_ECX]; + env->features[FEAT_8000_0007_EDX] &= ~minus_features[FEAT_8000_0007_EDX]; env->features[FEAT_C000_0001_EDX] &= ~minus_features[FEAT_C000_0001_EDX]; env->features[FEAT_KVM] &= ~minus_features[FEAT_KVM]; env->features[FEAT_SVM] &= ~minus_features[FEAT_SVM]; @@ -2333,6 +2352,12 @@ void cpu_x86_cpuid(CPUX86State *env, uin (AMD_ENC_ASSOC(L3_ASSOCIATIVITY) << 12) | \ (L3_LINES_PER_TAG << 8) | (L3_LINE_SIZE); break; + case 0x80000007: + *eax = 0; + *ebx = 0; + *ecx = 0; + *edx = env->features[FEAT_8000_0007_EDX]; + break; case 0x80000008: /* virtual & phys address size in low 2 bytes. */ /* XXX: This value must match the one used in the MMU code. */ @@ -2598,6 +2623,7 @@ static void x86_cpu_realizefn(DeviceStat ); env->features[FEAT_8000_0001_ECX] &= TCG_EXT3_FEATURES; env->features[FEAT_SVM] &= TCG_SVM_FEATURES; + env->features[FEAT_8000_0007_EDX] &= TCG_APM_FEATURES; } else { KVMState *s = kvm_state; if ((cpu->check_cpuid || cpu->enforce_cpuid) Index: qemu-invariant-tsc/target-i386/cpu.h =================================================================== --- qemu-invariant-tsc.orig/target-i386/cpu.h +++ qemu-invariant-tsc/target-i386/cpu.h @@ -398,6 +398,7 @@ typedef enum FeatureWord { FEAT_7_0_EBX, /* CPUID[EAX=7,ECX=0].EBX */ FEAT_8000_0001_EDX, /* CPUID[8000_0001].EDX */ FEAT_8000_0001_ECX, /* CPUID[8000_0001].ECX */ + FEAT_8000_0007_EDX, /* CPUID[8000_0007].EDX */ FEAT_C000_0001_EDX, /* CPUID[C000_0001].EDX */ FEAT_KVM, /* CPUID[4000_0001].EAX (KVM_CPUID_FEATURES) */ FEAT_SVM, /* CPUID[8000_000A].EDX */