| Message ID | 20160426225604.13567.55443.stgit@tlendack-t1.amdoffice.net (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On Tue, Apr 26, 2016 at 3:56 PM, Tom Lendacky <thomas.lendacky@amd.com> wrote: > For AMD processors that support PAT, set the write-protect cache mode > (_PAGE_CACHE_MODE_WP) entry to the actual write-protect value (x05). What's the purpose of using the WP memory type? --Andy -- To unsubscribe from this list: send the line "unsubscribe kvm" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
On 04/27/2016 09:33 AM, Andy Lutomirski wrote: > On Tue, Apr 26, 2016 at 3:56 PM, Tom Lendacky <thomas.lendacky@amd.com> wrote: >> For AMD processors that support PAT, set the write-protect cache mode >> (_PAGE_CACHE_MODE_WP) entry to the actual write-protect value (x05). > > What's the purpose of using the WP memory type? The WP memory type is used for encrypting or decrypting data "in place". The use of the WP on the source data will prevent any of the source data from being cached. Refer to section 7.10.8 "Encrypt-in-Place" in the AMD64 APM link provided in the cover letter. This memory type will be used in subsequent patches for this purpose. Thanks, Tom > > --Andy > -- To unsubscribe from this list: send the line "unsubscribe kvm" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
On Wed, Apr 27, 2016 at 7:44 AM, Tom Lendacky <thomas.lendacky@amd.com> wrote: > On 04/27/2016 09:33 AM, Andy Lutomirski wrote: >> On Tue, Apr 26, 2016 at 3:56 PM, Tom Lendacky <thomas.lendacky@amd.com> wrote: >>> For AMD processors that support PAT, set the write-protect cache mode >>> (_PAGE_CACHE_MODE_WP) entry to the actual write-protect value (x05). >> >> What's the purpose of using the WP memory type? > > The WP memory type is used for encrypting or decrypting data "in place". > The use of the WP on the source data will prevent any of the source > data from being cached. Refer to section 7.10.8 "Encrypt-in-Place" in > the AMD64 APM link provided in the cover letter. > > This memory type will be used in subsequent patches for this purpose. OK. Why AMD-only? I thought Intel supported WP, too. --Andy -- To unsubscribe from this list: send the line "unsubscribe kvm" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
On 04/27/2016 09:47 AM, Andy Lutomirski wrote: > On Wed, Apr 27, 2016 at 7:44 AM, Tom Lendacky <thomas.lendacky@amd.com> wrote: >> On 04/27/2016 09:33 AM, Andy Lutomirski wrote: >>> On Tue, Apr 26, 2016 at 3:56 PM, Tom Lendacky <thomas.lendacky@amd.com> wrote: >>>> For AMD processors that support PAT, set the write-protect cache mode >>>> (_PAGE_CACHE_MODE_WP) entry to the actual write-protect value (x05). >>> >>> What's the purpose of using the WP memory type? >> >> The WP memory type is used for encrypting or decrypting data "in place". >> The use of the WP on the source data will prevent any of the source >> data from being cached. Refer to section 7.10.8 "Encrypt-in-Place" in >> the AMD64 APM link provided in the cover letter. >> >> This memory type will be used in subsequent patches for this purpose. > > OK. > > Why AMD-only? I thought Intel supported WP, too. Just me being conservative. If there aren't any objections from the Intel folks about it we can remove the vendor check and just set it. Thanks, Tom > > --Andy > -- To unsubscribe from this list: send the line "unsubscribe kvm" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
On Wed, Apr 27, 2016 at 8:05 AM, Tom Lendacky <thomas.lendacky@amd.com> wrote: > On 04/27/2016 09:47 AM, Andy Lutomirski wrote: >> On Wed, Apr 27, 2016 at 7:44 AM, Tom Lendacky <thomas.lendacky@amd.com> wrote: >>> On 04/27/2016 09:33 AM, Andy Lutomirski wrote: >>>> On Tue, Apr 26, 2016 at 3:56 PM, Tom Lendacky <thomas.lendacky@amd.com> wrote: >>>>> For AMD processors that support PAT, set the write-protect cache mode >>>>> (_PAGE_CACHE_MODE_WP) entry to the actual write-protect value (x05). >>>> >>>> What's the purpose of using the WP memory type? >>> >>> The WP memory type is used for encrypting or decrypting data "in place". >>> The use of the WP on the source data will prevent any of the source >>> data from being cached. Refer to section 7.10.8 "Encrypt-in-Place" in >>> the AMD64 APM link provided in the cover letter. >>> >>> This memory type will be used in subsequent patches for this purpose. >> >> OK. >> >> Why AMD-only? I thought Intel supported WP, too. > > Just me being conservative. If there aren't any objections from the > Intel folks about it we can remove the vendor check and just set it. I think there are some errata that will cause high PAT references to incorrectly reference the low parts of the table, but I don't recall any that go the other way around. So merely setting WP in a high entry should be harmless unless something tries to use it. > > Thanks, > Tom > >> >> --Andy >>
On Wed, Apr 27, 2016 at 08:12:56AM -0700, Andy Lutomirski wrote:
> I think there are some errata
Isn't that addressed by the first branch of the if-test in pat_init():
if ((c->x86_vendor == X86_VENDOR_INTEL) &&
(((c->x86 == 0x6) && (c->x86_model <= 0xd)) ||
((c->x86 == 0xf) && (c->x86_model <= 0x6)))) {
On Wed, Apr 27, 2016 at 8:31 AM, Borislav Petkov <bp@alien8.de> wrote: > On Wed, Apr 27, 2016 at 08:12:56AM -0700, Andy Lutomirski wrote: >> I think there are some errata > > Isn't that addressed by the first branch of the if-test in pat_init(): > > if ((c->x86_vendor == X86_VENDOR_INTEL) && > (((c->x86 == 0x6) && (c->x86_model <= 0xd)) || > ((c->x86 == 0xf) && (c->x86_model <= 0x6)))) { > That's the intent, but I'm unconvinced that it's complete. The reason that WT is in slot 7 is that if it accidentally ends up using the slot 3 entry instead of 7 (e.g. if a 2M page gets confused due to an erratum we didn't handle or similar), then it falls back to UC, which is safe. But this is mostly moot in this case. There is no safe fallback for WP, but it doesn't really matter, because no one will actually try to use it except on a system will full PAT support anyway. So I'm not really concerned. > > -- > Regards/Gruss, > Boris. > > ECO tip #101: Trim your mails when you reply.
diff --git a/arch/x86/mm/pat.c b/arch/x86/mm/pat.c index fb0604f..dda78ed 100644 --- a/arch/x86/mm/pat.c +++ b/arch/x86/mm/pat.c @@ -345,6 +345,8 @@ void pat_init(void) * we lose performance without causing a correctness issue. * Pentium 4 erratum N46 is an example for such an erratum, * although we try not to use PAT at all on affected CPUs. + * AMD processors support write-protect so initialize the + * PAT slot 5 appropriately. * * PTE encoding: * PAT @@ -356,7 +358,7 @@ void pat_init(void) * 010 2 UC-: _PAGE_CACHE_MODE_UC_MINUS * 011 3 UC : _PAGE_CACHE_MODE_UC * 100 4 WB : Reserved - * 101 5 WC : Reserved + * 101 5 WC : Reserved (AMD: _PAGE_CACHE_MODE_WP) * 110 6 UC-: Reserved * 111 7 WT : _PAGE_CACHE_MODE_WT * @@ -364,7 +366,12 @@ void pat_init(void) * corresponding types in the presence of PAT errata. */ pat = PAT(0, WB) | PAT(1, WC) | PAT(2, UC_MINUS) | PAT(3, UC) | - PAT(4, WB) | PAT(5, WC) | PAT(6, UC_MINUS) | PAT(7, WT); + PAT(4, WB) | PAT(6, UC_MINUS) | PAT(7, WT); + + if (c->x86_vendor == X86_VENDOR_AMD) + pat |= PAT(5, WP); + else + pat |= PAT(5, WC); } if (!boot_cpu_done) {
For AMD processors that support PAT, set the write-protect cache mode (_PAGE_CACHE_MODE_WP) entry to the actual write-protect value (x05). Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com> --- arch/x86/mm/pat.c | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) -- To unsubscribe from this list: send the line "unsubscribe kvm" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html