From patchwork Thu Jul 7 17:24:53 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?UmFkaW0gS3LEjW3DocWZ?= X-Patchwork-Id: 9219317 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 7007E60467 for ; Thu, 7 Jul 2016 17:25:17 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 565C428410 for ; Thu, 7 Jul 2016 17:25:17 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 48A8728412; Thu, 7 Jul 2016 17:25:17 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.9 required=2.0 tests=BAYES_00,HK_RANDOM_FROM, RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id D6C8228410 for ; Thu, 7 Jul 2016 17:25:16 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752528AbcGGRZJ (ORCPT ); Thu, 7 Jul 2016 13:25:09 -0400 Received: from mx1.redhat.com ([209.132.183.28]:42715 "EHLO mx1.redhat.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751395AbcGGRZH (ORCPT ); Thu, 7 Jul 2016 13:25:07 -0400 Received: from int-mx11.intmail.prod.int.phx2.redhat.com (int-mx11.intmail.prod.int.phx2.redhat.com [10.5.11.24]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id 0E0AA6407A for ; Thu, 7 Jul 2016 17:25:02 +0000 (UTC) Received: from potion (dhcp-1-206.brq.redhat.com [10.34.1.206]) by int-mx11.intmail.prod.int.phx2.redhat.com (8.14.4/8.14.4) with SMTP id u67HOxxb025321; Thu, 7 Jul 2016 13:25:00 -0400 Received: by potion (sSMTP sendmail emulation); Thu, 07 Jul 2016 19:24:59 +0200 From: =?UTF-8?q?Radim=20Kr=C4=8Dm=C3=A1=C5=99?= To: kvm@vger.kernel.org Cc: Paolo Bonzini Subject: [kvm-unit-tests PATCH] x86: apic: APIC ID tests Date: Thu, 7 Jul 2016 19:24:53 +0200 Message-Id: <20160707172453.15642-1-rkrcmar@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.68 on 10.5.11.24 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.38]); Thu, 07 Jul 2016 17:25:02 +0000 (UTC) Sender: kvm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP KVM commit 000000000000 ("KVM: x86: reset xAPIC ID") fixed xAPIC ID value after reset. QEMU commit 5232d00a041c ("target-i386: Implement CPUID[0xB] (Extended Topology Enumeration)") added initial x2APIC to CPUID. KVM commit 000000000000 ("KVM: x86: use hardware-compatible format for APIC ID register") changed internal format of APIC ID register, so make sure that guest-visible APIC ID was not been affected. Signed-off-by: Radim Krčmář --- I'll send v2 with hashes when KVM patches are merged. Should I remove the hunk that depends on QEMU version? (It introduces a FAIL.) lib/x86/apic.c | 9 +++++++++ lib/x86/apic.h | 1 + x86/apic.c | 57 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 67 insertions(+) diff --git a/lib/x86/apic.c b/lib/x86/apic.c index 2ceba395e0dc..a9ed28d67727 100644 --- a/lib/x86/apic.c +++ b/lib/x86/apic.c @@ -1,6 +1,7 @@ #include "libcflat.h" #include "apic.h" #include "msr.h" +#include "processor.h" static void *g_apic = (void *)0xfee00000; static void *g_ioapic = (void *)0xfec00000; @@ -129,6 +130,14 @@ int enable_x2apic(void) } } +void reset_apic(void) +{ + u64 disabled = rdmsr(MSR_IA32_APICBASE) & ~(APIC_EN | APIC_EXTD); + wrmsr(MSR_IA32_APICBASE, disabled); + apic_ops = &xapic_ops; + wrmsr(MSR_IA32_APICBASE, disabled | APIC_EN); +} + u32 ioapic_read_reg(unsigned reg) { *(volatile u32 *)g_ioapic = reg; diff --git a/lib/x86/apic.h b/lib/x86/apic.h index 2d0504c2088d..dbd6c9b6e7e4 100644 --- a/lib/x86/apic.h +++ b/lib/x86/apic.h @@ -37,5 +37,6 @@ void apic_icr_write(uint32_t val, uint32_t dest); uint32_t apic_id(void); int enable_x2apic(void); +void reset_apic(void); #endif diff --git a/x86/apic.c b/x86/apic.c index 8b08a950a0c7..5fc83c681ce8 100644 --- a/x86/apic.c +++ b/x86/apic.c @@ -136,6 +136,62 @@ static void test_apicbase(void) report_prefix_pop(); } +static void do_write_apic_id(void *id) +{ + apic_write(APIC_ID, *(u32 *)id); +} + +static void __test_apic_id(void * unused) +{ + u32 id, newid; + u8 initial_xapic_id = cpuid(1).b >> 24; + u32 initial_x2apic_id = cpuid(0xb).d; + bool x2apic_mode = rdmsr(MSR_IA32_APICBASE) & APIC_EXTD; + + if (x2apic_mode) + reset_apic(); + + id = apic_id(); + report("xapic id matches cpuid", initial_xapic_id == id); + + newid = (id + 1) << 24; + report("writeable xapic id", + !test_for_exception(GP_VECTOR, do_write_apic_id, &newid) && + id + 1 == apic_id()); + + if (!enable_x2apic()) + goto out; + + report("non-writeable x2apic id", + test_for_exception(GP_VECTOR, do_write_apic_id, &newid)); + report("sane x2apic id", initial_xapic_id == (apic_id() & 0xff)); + + /* old QEMUs do not set initial x2APIC ID */ + report("x2apic id matches cpuid", + initial_xapic_id == (initial_x2apic_id & 0xff) && + initial_x2apic_id == apic_id()); + +out: + reset_apic(); + + report("correct xapic id after reset", initial_xapic_id == apic_id()); + + /* old KVMs do not reset xAPIC ID */ + if (id != apic_id()) + apic_write(APIC_ID, id << 24); + + if (x2apic_mode) + enable_x2apic(); +} + +static void test_apic_id(void) +{ + if (cpu_count() < 2) + return; + + on_cpu(1, __test_apic_id, NULL); +} + static int ipi_count; static void self_ipi_isr(isr_regs_t *regs) @@ -303,6 +359,7 @@ int main() test_lapic_existence(); mask_pic_interrupts(); + test_apic_id(); test_enable_x2apic(); test_apicbase();