From patchwork Tue Sep 27 18:05:51 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christoffer Dall X-Patchwork-Id: 9352513 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id DECF56086A for ; Tue, 27 Sep 2016 18:07:34 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id D6A542924F for ; Tue, 27 Sep 2016 18:07:34 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id CBD3129260; Tue, 27 Sep 2016 18:07:34 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.8 required=2.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_HI,T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 1FE102924F for ; Tue, 27 Sep 2016 18:07:34 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S936516AbcI0SH2 (ORCPT ); Tue, 27 Sep 2016 14:07:28 -0400 Received: from mail-wm0-f53.google.com ([74.125.82.53]:38334 "EHLO mail-wm0-f53.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S935513AbcI0SGa (ORCPT ); Tue, 27 Sep 2016 14:06:30 -0400 Received: by mail-wm0-f53.google.com with SMTP id l132so26963724wmf.1 for ; Tue, 27 Sep 2016 11:06:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=R8+ujOEncmMgUP8iSQKo4fOVaMZv5hSVCgj8nm1JbmA=; b=H/lHV9TKqjq7ib4YjVAqgF+AGUHVZpQui6NRV9Heqp5Ux/NccbzNPHLfvL3Jy0OcRJ mZQ7YHCAAhtdLaBrUBXKZiMCSydWgmjdXDAlJ04olUqWYrblgfSSqGJHaFcPUzPqvzPB RxQLPve56oC/KLZ0R35KtbJq3TOQaJtltpTzY= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=R8+ujOEncmMgUP8iSQKo4fOVaMZv5hSVCgj8nm1JbmA=; b=YTZwvGLyP291PYrvh/xMiLOhtEvFVvviipnr6pnjOsn8/YFwAJU/UlEG06kFLo2Gxf my2EpY2I88IGsiEE4IuWKdD/hnOWhsKtUrUj+7awaluLiR7w0hsz+aOWgAdnIWUlHLhW 0VJCUvzZZtPD2g3z/1NPVGwzqwj5pOMqL9OdWMgudWclXbBjKYceJ7MCSLH7yZC161mA OwRkFCIO0+Tg2YhNuGraHXVEceXBuuAP0IzriCBPrqMWo9Cg9w18+ZOF65RhaaWm3yjj CdKSR9EH9GhYt8KbGXyn7z0z8+RqVnKa98OeAh8Kd0BoDY4jcvF4bhzTwrrHJQO3hMEv BXvQ== X-Gm-Message-State: AA6/9RncC9pDW4jvJVluD/teE+fR5+6BHRtrHAzBTdM5Hk1fWCmnOIj7CbxNXl0JK8sw+f/S X-Received: by 10.28.125.209 with SMTP id y200mr4419898wmc.112.1474999589585; Tue, 27 Sep 2016 11:06:29 -0700 (PDT) Received: from localhost.localdomain ([94.18.191.146]) by smtp.gmail.com with ESMTPSA id k2sm17932539wmg.23.2016.09.27.11.06.28 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 27 Sep 2016 11:06:29 -0700 (PDT) From: Christoffer Dall To: Paolo Bonzini , =?UTF-8?q?Radim=20Kr=C4=8Dm=C3=A1=C5=99?= Cc: Marc Zyngier , kvmarm@lists.cs.columbia.edu, kvm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Vladimir Murzin , Russell King , Christoffer Dall Subject: [PULL 43/50] ARM: Introduce MPIDR_LEVEL_SHIFT macro Date: Tue, 27 Sep 2016 20:05:51 +0200 Message-Id: <20160927180558.14699-44-christoffer.dall@linaro.org> X-Mailer: git-send-email 2.9.0 In-Reply-To: <20160927180558.14699-1-christoffer.dall@linaro.org> References: <20160927180558.14699-1-christoffer.dall@linaro.org> Sender: kvm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Vladimir Murzin vgic-v3 driver uses architecture specific MPIDR_LEVEL_SHIFT macro to encode the affinity in a form compatible with ICC_SGI* registers. Unfortunately, that macro is missing on ARM, so let's add it. Cc: Russell King Acked-by: Marc Zyngier Signed-off-by: Vladimir Murzin Signed-off-by: Christoffer Dall --- arch/arm/include/asm/cputype.h | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/include/asm/cputype.h b/arch/arm/include/asm/cputype.h index 1ee94c7..e2d94c1 100644 --- a/arch/arm/include/asm/cputype.h +++ b/arch/arm/include/asm/cputype.h @@ -55,6 +55,7 @@ #define MPIDR_LEVEL_BITS 8 #define MPIDR_LEVEL_MASK ((1 << MPIDR_LEVEL_BITS) - 1) +#define MPIDR_LEVEL_SHIFT(level) (MPIDR_LEVEL_BITS * level) #define MPIDR_AFFINITY_LEVEL(mpidr, level) \ ((mpidr >> (MPIDR_LEVEL_BITS * level)) & MPIDR_LEVEL_MASK)