From patchwork Fri Nov 4 17:31:56 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 9412975 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 40A2F6022E for ; Fri, 4 Nov 2016 17:31:59 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 30A0B2ADFB for ; Fri, 4 Nov 2016 17:31:59 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 2562A2B173; Fri, 4 Nov 2016 17:31:59 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=2.0 tests=BAYES_00,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 9B89B2ADFB for ; Fri, 4 Nov 2016 17:31:58 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S935038AbcKDRby (ORCPT ); Fri, 4 Nov 2016 13:31:54 -0400 Received: from foss.arm.com ([217.140.101.70]:36642 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S936485AbcKDRbu (ORCPT ); Fri, 4 Nov 2016 13:31:50 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id C68B6164F; Fri, 4 Nov 2016 10:31:49 -0700 (PDT) Received: from e104803-lin.lan (unknown [10.1.207.46]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id A08CC3F318; Fri, 4 Nov 2016 10:31:48 -0700 (PDT) From: Andre Przywara To: Will Deacon Cc: Marc Zyngier , kvmarm@lists.cs.columbia.edu, kvm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Vladimir Murzin Subject: [PATCH v8 09/16] arm: allow creation of an MSI register frame region Date: Fri, 4 Nov 2016 17:31:56 +0000 Message-Id: <20161104173203.21168-10-andre.przywara@arm.com> X-Mailer: git-send-email 2.9.0 In-Reply-To: <20161104173203.21168-1-andre.przywara@arm.com> References: <20161104173203.21168-1-andre.przywara@arm.com> Sender: kvm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP The GICv3 ITS expects a separate 64K page to hold ITS registers. Add a function to reserve such a page in the guest's I/O memory and use that for the ITS vGIC type. Signed-off-by: Andre Przywara --- arm/gic.c | 63 ++++++++++++++++++++++++++++++++++++++++++++ arm/include/arm-common/gic.h | 1 + 2 files changed, 64 insertions(+) diff --git a/arm/gic.c b/arm/gic.c index 4d12f31..ed9016d 100644 --- a/arm/gic.c +++ b/arm/gic.c @@ -8,6 +8,7 @@ #include #include #include +#include /* Those names are not defined for ARM (yet) */ #ifndef KVM_VGIC_V3_ADDR_TYPE_DIST @@ -29,6 +30,8 @@ static int gic_fd = -1; static u64 gic_redists_base; static u64 gic_redists_size; +static u64 gic_msi_base; +static u64 gic_msi_size = 0; int irqchip_parser(const struct option *opt, const char *arg, int unset) { @@ -46,6 +49,56 @@ int irqchip_parser(const struct option *opt, const char *arg, int unset) return 0; } +static int gic__create_its_frame(struct kvm *kvm, u64 its_frame_addr) +{ + struct kvm_create_device its_device = { + .type = KVM_DEV_TYPE_ARM_VGIC_ITS, + .flags = 0, + }; + struct kvm_device_attr its_attr = { + .group = KVM_DEV_ARM_VGIC_GRP_ADDR, + .attr = KVM_VGIC_ITS_ADDR_TYPE, + .addr = (u64)(unsigned long)&its_frame_addr, + }; + struct kvm_device_attr its_init_attr = { + .group = KVM_DEV_ARM_VGIC_GRP_CTRL, + .attr = KVM_DEV_ARM_VGIC_CTRL_INIT, + }; + int err; + + err = ioctl(kvm->vm_fd, KVM_CREATE_DEVICE, &its_device); + if (err) { + fprintf(stderr, + "GICv3 ITS requested, but kernel does not support it.\n"); + fprintf(stderr, "Try --irqchip=gicv3 instead\n"); + return err; + } + + err = ioctl(its_device.fd, KVM_HAS_DEVICE_ATTR, &its_attr); + if (err) { + close(its_device.fd); + its_device.fd = -1; + return err; + } + + err = ioctl(its_device.fd, KVM_SET_DEVICE_ATTR, &its_attr); + if (err) + return err; + + return ioctl(its_device.fd, KVM_SET_DEVICE_ATTR, &its_init_attr); +} + +static int gic__create_msi_frame(struct kvm *kvm, enum irqchip_type type, + u64 msi_frame_addr) +{ + switch (type) { + case IRQCHIP_GICV3_ITS: + return gic__create_its_frame(kvm, msi_frame_addr); + default: /* No MSI frame needed */ + return 0; + } +} + static int gic__create_device(struct kvm *kvm, enum irqchip_type type) { int err; @@ -75,6 +128,7 @@ static int gic__create_device(struct kvm *kvm, enum irqchip_type type) dist_attr.attr = KVM_VGIC_V2_ADDR_TYPE_DIST; break; case IRQCHIP_GICV3: + case IRQCHIP_GICV3_ITS: gic_device.type = KVM_DEV_TYPE_ARM_VGIC_V3; dist_attr.attr = KVM_VGIC_V3_ADDR_TYPE_DIST; break; @@ -90,6 +144,7 @@ static int gic__create_device(struct kvm *kvm, enum irqchip_type type) case IRQCHIP_GICV2: err = ioctl(gic_fd, KVM_SET_DEVICE_ATTR, &cpu_if_attr); break; + case IRQCHIP_GICV3_ITS: case IRQCHIP_GICV3: err = ioctl(gic_fd, KVM_SET_DEVICE_ATTR, &redist_attr); break; @@ -101,6 +156,10 @@ static int gic__create_device(struct kvm *kvm, enum irqchip_type type) if (err) goto out_err; + err = gic__create_msi_frame(kvm, type, gic_msi_base); + if (err) + goto out_err; + return 0; out_err: @@ -144,9 +203,13 @@ int gic__create(struct kvm *kvm, enum irqchip_type type) switch (type) { case IRQCHIP_GICV2: break; + case IRQCHIP_GICV3_ITS: + gic_msi_size = KVM_VGIC_V3_ITS_SIZE; + /* fall through */ case IRQCHIP_GICV3: gic_redists_size = kvm->cfg.nrcpus * ARM_GIC_REDIST_SIZE; gic_redists_base = ARM_GIC_DIST_BASE - gic_redists_size; + gic_msi_base = gic_redists_base - gic_msi_size; break; default: return -ENODEV; diff --git a/arm/include/arm-common/gic.h b/arm/include/arm-common/gic.h index b43a180..433dd23 100644 --- a/arm/include/arm-common/gic.h +++ b/arm/include/arm-common/gic.h @@ -24,6 +24,7 @@ enum irqchip_type { IRQCHIP_GICV2, IRQCHIP_GICV3, + IRQCHIP_GICV3_ITS, }; struct kvm;