From patchwork Thu Dec 29 22:43:31 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christopher Covington X-Patchwork-Id: 9491657 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 34A4B60453 for ; Thu, 29 Dec 2016 22:45:17 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 2044E1FF15 for ; Thu, 29 Dec 2016 22:45:17 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 121A020649; Thu, 29 Dec 2016 22:45:17 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.8 required=2.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_HI,T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 9FFE41FF15 for ; Thu, 29 Dec 2016 22:45:16 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751336AbcL2Wnp (ORCPT ); Thu, 29 Dec 2016 17:43:45 -0500 Received: from smtp.codeaurora.org ([198.145.29.96]:46326 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750875AbcL2Wno (ORCPT ); Thu, 29 Dec 2016 17:43:44 -0500 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id E1FF06027F; Thu, 29 Dec 2016 22:43:43 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1483051423; bh=Va0vRuCR1RZcFfPL5aY2kGT+pAlzAnyJHdpH7g1cQpg=; h=From:To:Cc:Subject:Date:From; b=dByI3JzolRw0lbL13slm8Pka9PTd1sgzYM+fEVsFvwor1kUZcpjUEkw5s2xf6iCFv AxDs7j3IDvo5UMhpB2wEtpgtGgOXt8wj2a91f2+tHj2JAMRbwLTJ66Fq7NSc2tuipr SiVyV64x8nZob9Ic5YjXsG7N7n/NKooNtThk7FhI= Received: from illium.qualcomm.com (global_nat1_iad_fw.qualcomm.com [129.46.232.65]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: cov@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id 04E6C6027F; Thu, 29 Dec 2016 22:43:41 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1483051423; bh=Va0vRuCR1RZcFfPL5aY2kGT+pAlzAnyJHdpH7g1cQpg=; h=From:To:Cc:Subject:Date:From; b=dByI3JzolRw0lbL13slm8Pka9PTd1sgzYM+fEVsFvwor1kUZcpjUEkw5s2xf6iCFv AxDs7j3IDvo5UMhpB2wEtpgtGgOXt8wj2a91f2+tHj2JAMRbwLTJ66Fq7NSc2tuipr SiVyV64x8nZob9Ic5YjXsG7N7n/NKooNtThk7FhI= DMARC-Filter: OpenDMARC Filter v1.3.1 smtp.codeaurora.org 04E6C6027F Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=pass smtp.mailfrom=cov@codeaurora.org From: Christopher Covington To: Paolo Bonzini , =?UTF-8?q?Radim=20Kr=C4=8Dm=C3=A1=C5=99?= , Christoffer Dall , Marc Zyngier , Catalin Marinas , Will Deacon , kvm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, kvmarm@lists.cs.columbia.edu, linux-kernel@vger.kernel.org, shankerd@codeaurora.org, timur@codeaurora.org Cc: Christopher Covington Subject: [PATCH v2 1/5] arm64: Define Falkor v1 CPU Date: Thu, 29 Dec 2016 17:43:31 -0500 Message-Id: <20161229224335.13531-1-cov@codeaurora.org> X-Mailer: git-send-email 2.9.3 Sender: kvm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Shanker Donthineni Define the MIDR implementer and part number field values for the Qualcomm Datacenter Technologies Falkor processor version 1 in the usual manner. Signed-off-by: Shanker Donthineni Signed-off-by: Christopher Covington --- arch/arm64/include/asm/cputype.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/include/asm/cputype.h b/arch/arm64/include/asm/cputype.h index 26a68dd..ee60561 100644 --- a/arch/arm64/include/asm/cputype.h +++ b/arch/arm64/include/asm/cputype.h @@ -71,6 +71,7 @@ #define ARM_CPU_IMP_APM 0x50 #define ARM_CPU_IMP_CAVIUM 0x43 #define ARM_CPU_IMP_BRCM 0x42 +#define ARM_CPU_IMP_QCOM 0x51 #define ARM_CPU_PART_AEM_V8 0xD0F #define ARM_CPU_PART_FOUNDATION 0xD00 @@ -84,10 +85,13 @@ #define BRCM_CPU_PART_VULCAN 0x516 +#define QCOM_CPU_PART_FALKOR_V1 0x800 + #define MIDR_CORTEX_A53 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A53) #define MIDR_CORTEX_A57 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A57) #define MIDR_THUNDERX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX) #define MIDR_THUNDERX_81XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_81XX) +#define MIDR_QCOM_FALKOR_V1 MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, QCOM_CPU_PART_FALKOR_V1) #ifndef __ASSEMBLY__