From patchwork Thu Feb 2 16:32:18 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 9552431 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id EA0AC60236 for ; Thu, 2 Feb 2017 16:31:30 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id D7FDA28174 for ; Thu, 2 Feb 2017 16:31:30 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id CBF2E2847D; Thu, 2 Feb 2017 16:31:30 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=2.0 tests=BAYES_00,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 520D428174 for ; Thu, 2 Feb 2017 16:31:30 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752116AbdBBQb3 (ORCPT ); Thu, 2 Feb 2017 11:31:29 -0500 Received: from foss.arm.com ([217.140.101.70]:33486 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752096AbdBBQb0 (ORCPT ); Thu, 2 Feb 2017 11:31:26 -0500 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 617AE1688; Thu, 2 Feb 2017 08:31:26 -0800 (PST) Received: from e104803-lin.lan (unknown [10.1.207.46]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 5F6403F24D; Thu, 2 Feb 2017 08:31:25 -0800 (PST) From: Andre Przywara To: Will Deacon , Marc Zyngier Cc: Vladimir Murzin , kvmarm@lists.cs.columbia.edu, kvm@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [kvmtool PATCH v9 10/15] arm: FDT: create MSI controller DT node Date: Thu, 2 Feb 2017 16:32:18 +0000 Message-Id: <20170202163223.15372-11-andre.przywara@arm.com> X-Mailer: git-send-email 2.9.0 In-Reply-To: <20170202163223.15372-1-andre.przywara@arm.com> References: <20170202163223.15372-1-andre.przywara@arm.com> Sender: kvm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP The ARM GICv3 ITS requires a separate device tree node to describe the ITS. Add this as a child to the GIC interrupt controller node to let a guest discover and use the ITS if the user requests it. Since we now need to specify #address-cells for the GIC node, we have to add two zeroes to the interrupt map to match that. Signed-off-by: Andre Przywara --- arm/gic.c | 22 +++++++++++++++++++++- arm/include/arm-common/fdt-arch.h | 2 +- arm/pci.c | 5 +++++ 3 files changed, 27 insertions(+), 2 deletions(-) diff --git a/arm/gic.c b/arm/gic.c index 78fd583..c8478a3 100644 --- a/arm/gic.c +++ b/arm/gic.c @@ -250,7 +250,8 @@ late_init(gic__init_gic) void gic__generate_fdt_nodes(void *fdt, enum irqchip_type type) { - const char *compatible; + const char *compatible, *msi_compatible = NULL; + u64 msi_prop[2]; u64 reg_prop[] = { cpu_to_fdt64(ARM_GIC_DIST_BASE), cpu_to_fdt64(ARM_GIC_DIST_SIZE), 0, 0, /* to be filled */ @@ -262,6 +263,9 @@ void gic__generate_fdt_nodes(void *fdt, enum irqchip_type type) reg_prop[2] = cpu_to_fdt64(ARM_GIC_CPUI_BASE); reg_prop[3] = cpu_to_fdt64(ARM_GIC_CPUI_SIZE); break; + case IRQCHIP_GICV3_ITS: + msi_compatible = "arm,gic-v3-its"; + /* fall-through */ case IRQCHIP_GICV3: compatible = "arm,gic-v3"; reg_prop[2] = cpu_to_fdt64(gic_redists_base); @@ -277,6 +281,22 @@ void gic__generate_fdt_nodes(void *fdt, enum irqchip_type type) _FDT(fdt_property(fdt, "interrupt-controller", NULL, 0)); _FDT(fdt_property(fdt, "reg", reg_prop, sizeof(reg_prop))); _FDT(fdt_property_cell(fdt, "phandle", PHANDLE_GIC)); + _FDT(fdt_property_cell(fdt, "#address-cells", 2)); + _FDT(fdt_property_cell(fdt, "#size-cells", 2)); + + if (msi_compatible) { + _FDT(fdt_property(fdt, "ranges", NULL, 0)); + + _FDT(fdt_begin_node(fdt, "msic")); + _FDT(fdt_property_string(fdt, "compatible", msi_compatible)); + _FDT(fdt_property(fdt, "msi-controller", NULL, 0)); + _FDT(fdt_property_cell(fdt, "phandle", PHANDLE_MSI)); + msi_prop[0] = cpu_to_fdt64(gic_msi_base); + msi_prop[1] = cpu_to_fdt64(gic_msi_size); + _FDT(fdt_property(fdt, "reg", msi_prop, sizeof(msi_prop))); + _FDT(fdt_end_node(fdt)); + } + _FDT(fdt_end_node(fdt)); } diff --git a/arm/include/arm-common/fdt-arch.h b/arm/include/arm-common/fdt-arch.h index 53ba633..60c2d40 100644 --- a/arm/include/arm-common/fdt-arch.h +++ b/arm/include/arm-common/fdt-arch.h @@ -1,6 +1,6 @@ #ifndef ARM__FDT_H #define ARM__FDT_H -enum phandles {PHANDLE_RESERVED = 0, PHANDLE_GIC, PHANDLES_MAX}; +enum phandles {PHANDLE_RESERVED = 0, PHANDLE_GIC, PHANDLE_MSI, PHANDLES_MAX}; #endif /* ARM__FDT_H */ diff --git a/arm/pci.c b/arm/pci.c index 2bc718e..37145cc 100644 --- a/arm/pci.c +++ b/arm/pci.c @@ -18,6 +18,8 @@ struct of_gic_irq { struct of_interrupt_map_entry { struct of_pci_irq_mask pci_irq_mask; u32 gic_phandle; + u32 gic_addr_hi; + u32 gic_addr_lo; struct of_gic_irq gic_irq; } __attribute__((packed)); @@ -64,6 +66,7 @@ void pci__generate_fdt_nodes(void *fdt) _FDT(fdt_property(fdt, "bus-range", bus_range, sizeof(bus_range))); _FDT(fdt_property(fdt, "reg", &cfg_reg_prop, sizeof(cfg_reg_prop))); _FDT(fdt_property(fdt, "ranges", ranges, sizeof(ranges))); + _FDT(fdt_property_cell(fdt, "msi-parent", PHANDLE_MSI)); /* Generate the interrupt map ... */ dev_hdr = device__first_dev(DEVICE_BUS_PCI); @@ -84,6 +87,8 @@ void pci__generate_fdt_nodes(void *fdt) .pci_pin = cpu_to_fdt32(pin), }, .gic_phandle = cpu_to_fdt32(PHANDLE_GIC), + .gic_addr_hi = 0, + .gic_addr_lo = 0, .gic_irq = { .type = cpu_to_fdt32(GIC_FDT_IRQ_TYPE_SPI), .num = cpu_to_fdt32(irq - GIC_SPI_IRQ_BASE),