Message ID | 20170216154225.19244.96438.stgit@tlendack-t1.amdoffice.net (mailing list archive) |
---|---|
State | New, archived |
Headers | show |
On Thu, Feb 16, 2017 at 09:42:25AM -0600, Tom Lendacky wrote: > For processors that support PAT, set the write-protect cache mode > (_PAGE_CACHE_MODE_WP) entry to the actual write-protect value (x05). > > Acked-by: Borislav Petkov <bp@suse.de> > Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com> Just a nit: Subject should have "x86/mm/pat: " prefix but that can be fixed when applying.
On 2/17/2017 5:07 AM, Borislav Petkov wrote: > On Thu, Feb 16, 2017 at 09:42:25AM -0600, Tom Lendacky wrote: >> For processors that support PAT, set the write-protect cache mode >> (_PAGE_CACHE_MODE_WP) entry to the actual write-protect value (x05). >> >> Acked-by: Borislav Petkov <bp@suse.de> >> Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com> > > Just a nit: > > Subject should have "x86/mm/pat: " prefix but that can be fixed when > applying. I'll go through the series and verify/fix the prefix for each patch. Thanks, Tom >
diff --git a/arch/x86/mm/pat.c b/arch/x86/mm/pat.c index 9b78685..6753d9c 100644 --- a/arch/x86/mm/pat.c +++ b/arch/x86/mm/pat.c @@ -295,7 +295,7 @@ static void init_cache_modes(void) * pat_init - Initialize PAT MSR and PAT table * * This function initializes PAT MSR and PAT table with an OS-defined value - * to enable additional cache attributes, WC and WT. + * to enable additional cache attributes, WC, WT and WP. * * This function must be called on all CPUs using the specific sequence of * operations defined in Intel SDM. mtrr_rendezvous_handler() provides this @@ -356,7 +356,7 @@ void pat_init(void) * 010 2 UC-: _PAGE_CACHE_MODE_UC_MINUS * 011 3 UC : _PAGE_CACHE_MODE_UC * 100 4 WB : Reserved - * 101 5 WC : Reserved + * 101 5 WP : _PAGE_CACHE_MODE_WP * 110 6 UC-: Reserved * 111 7 WT : _PAGE_CACHE_MODE_WT * @@ -364,7 +364,7 @@ void pat_init(void) * corresponding types in the presence of PAT errata. */ pat = PAT(0, WB) | PAT(1, WC) | PAT(2, UC_MINUS) | PAT(3, UC) | - PAT(4, WB) | PAT(5, WC) | PAT(6, UC_MINUS) | PAT(7, WT); + PAT(4, WB) | PAT(5, WP) | PAT(6, UC_MINUS) | PAT(7, WT); } if (!boot_cpu_done) {