From patchwork Fri Jan 12 12:07:36 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christoffer Dall X-Patchwork-Id: 10160449 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 0B863602D8 for ; Fri, 12 Jan 2018 12:09:17 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id E3A9C28518 for ; Fri, 12 Jan 2018 12:09:16 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id D87E3289CD; Fri, 12 Jan 2018 12:09:16 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.0 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 4461C28518 for ; Fri, 12 Jan 2018 12:09:16 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S933719AbeALMIl (ORCPT ); Fri, 12 Jan 2018 07:08:41 -0500 Received: from mail-wm0-f65.google.com ([74.125.82.65]:44650 "EHLO mail-wm0-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S933653AbeALMIi (ORCPT ); Fri, 12 Jan 2018 07:08:38 -0500 Received: by mail-wm0-f65.google.com with SMTP id t8so11613007wmc.3 for ; Fri, 12 Jan 2018 04:08:37 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=UAKjM00gFFHoD2dzRr/VnYuKJrxdM9djTyJa7vhtAL0=; b=D0XI3k9uSLhmp5RgSHpzTfXaN/2RSYrm7RKnfJBrXAycKz3kV21jnIdxeXuYWBZzYs xMxuTmNQwYGfXtbMbsMbbntWTYrmdDHS/MEdOaHhDuUnYWD7sgTgRzl6AWGrBNj1U727 vKdtyXQMgULeyz0byR+Ym10E9mLlSoZkbY8x0= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=UAKjM00gFFHoD2dzRr/VnYuKJrxdM9djTyJa7vhtAL0=; b=rq8n0BgpoqQNrVEXYkf3UGL2AAAk2JYOgGQSGlQ17XoQbGItKwLUu/As6MI/juGzqj vMYtAVpfVnysC/Lae5cKPCQgvR09WHhvTnRpvxVcpSfmFn8DPhIOn+7jc9jGN3PcmOM5 MlAJOrOowVf15MMW3zQviRYntM9KfyJ+agug4adG3sC8B9SvEJF0BFnZwPPmKT4vtRpe FWvKRsxlv8b3E4V93riLeRB+Ez5/UsAX1lWPda2HdbJ5nK6/EiKPHcdBO9MdAJoNsYj5 +XV0KIr3ErftAQ55o85E1miZ/TjUcOYh1REpc64/fMOOCM9OdzDk3WmxD0tnIvZ3W6YY /qow== X-Gm-Message-State: AKGB3mJwbfOnCxUw+Ifaf8JMPHq2r0ztKEZOcerGS5hLw/InSTPpiOZt IHLFqz89mU+Qqbh6jdQ4E4P8Xw== X-Google-Smtp-Source: ACJfBosuLXIr0NaNZdCTkO2KRZwm8Vkt8JzCMD9U7BQ3E8xRzuF//28uuKgnlxQ5KhWzvmqyjRzDog== X-Received: by 10.80.169.104 with SMTP id m37mr35036868edc.15.1515758916824; Fri, 12 Jan 2018 04:08:36 -0800 (PST) Received: from localhost.localdomain (x50d2404e.cust.hiper.dk. [80.210.64.78]) by smtp.gmail.com with ESMTPSA id f16sm13489705edj.65.2018.01.12.04.08.35 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 12 Jan 2018 04:08:36 -0800 (PST) From: Christoffer Dall To: kvmarm@lists.cs.columbia.edu, linux-arm-kernel@lists.infradead.org Cc: kvm@vger.kernel.org, Marc Zyngier , Shih-Wei Li , Andrew Jones , Christoffer Dall Subject: [PATCH v3 30/41] KVM: arm64: Prepare to handle deferred save/restore of 32-bit registers Date: Fri, 12 Jan 2018 13:07:36 +0100 Message-Id: <20180112120747.27999-31-christoffer.dall@linaro.org> X-Mailer: git-send-email 2.14.2 In-Reply-To: <20180112120747.27999-1-christoffer.dall@linaro.org> References: <20180112120747.27999-1-christoffer.dall@linaro.org> Sender: kvm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP 32-bit registers are not used by a 64-bit host kernel and can be deferred, but we need to rework the accesses to this register to access the latest value depending on whether or not guest system registers are loaded on the CPU or only reside in memory. Signed-off-by: Christoffer Dall Reviewed-by: Julien Thierry --- arch/arm64/include/asm/kvm_emulate.h | 32 +++++------------- arch/arm64/kvm/regmap.c | 65 ++++++++++++++++++++++++++---------- arch/arm64/kvm/sys_regs.c | 6 ++-- 3 files changed, 60 insertions(+), 43 deletions(-) diff --git a/arch/arm64/include/asm/kvm_emulate.h b/arch/arm64/include/asm/kvm_emulate.h index c9ca2dc579c7..a27610185906 100644 --- a/arch/arm64/include/asm/kvm_emulate.h +++ b/arch/arm64/include/asm/kvm_emulate.h @@ -33,7 +33,8 @@ #include unsigned long *vcpu_reg32(const struct kvm_vcpu *vcpu, u8 reg_num); -unsigned long *vcpu_spsr32(const struct kvm_vcpu *vcpu); +unsigned long vcpu_read_spsr32(const struct kvm_vcpu *vcpu); +void vcpu_write_spsr32(struct kvm_vcpu *vcpu, unsigned long v); bool kvm_condition_valid32(const struct kvm_vcpu *vcpu); void kvm_skip_instr32(struct kvm_vcpu *vcpu, bool is_wide_instr); @@ -150,41 +151,26 @@ static inline void vcpu_set_reg(struct kvm_vcpu *vcpu, u8 reg_num, static inline unsigned long vcpu_read_spsr(const struct kvm_vcpu *vcpu) { - unsigned long *p = (unsigned long *)&vcpu_gp_regs(vcpu)->spsr[KVM_SPSR_EL1]; - - if (vcpu_mode_is_32bit(vcpu)) { - unsigned long *p_32bit = vcpu_spsr32(vcpu); - - /* KVM_SPSR_SVC aliases KVM_SPSR_EL1 */ - if (p_32bit != (unsigned long *)p) - return *p_32bit; - } + if (vcpu_mode_is_32bit(vcpu)) + return vcpu_read_spsr32(vcpu); if (vcpu->arch.sysregs_loaded_on_cpu) return read_sysreg_el1(spsr); else - return *p; + return vcpu_gp_regs(vcpu)->spsr[KVM_SPSR_EL1]; } -static inline void vcpu_write_spsr(const struct kvm_vcpu *vcpu, unsigned long v) +static inline void vcpu_write_spsr(struct kvm_vcpu *vcpu, unsigned long v) { - unsigned long *p = (unsigned long *)&vcpu_gp_regs(vcpu)->spsr[KVM_SPSR_EL1]; - - /* KVM_SPSR_SVC aliases KVM_SPSR_EL1 */ if (vcpu_mode_is_32bit(vcpu)) { - unsigned long *p_32bit = vcpu_spsr32(vcpu); - - /* KVM_SPSR_SVC aliases KVM_SPSR_EL1 */ - if (p_32bit != (unsigned long *)p) { - *p_32bit = v; - return; - } + vcpu_write_spsr32(vcpu, v); + return; } if (vcpu->arch.sysregs_loaded_on_cpu) write_sysreg_el1(v, spsr); else - *p = v; + vcpu_gp_regs(vcpu)->spsr[KVM_SPSR_EL1] = v; } static inline bool vcpu_mode_priv(const struct kvm_vcpu *vcpu) diff --git a/arch/arm64/kvm/regmap.c b/arch/arm64/kvm/regmap.c index bbc6ae32e4af..3f65098aff8d 100644 --- a/arch/arm64/kvm/regmap.c +++ b/arch/arm64/kvm/regmap.c @@ -141,28 +141,59 @@ unsigned long *vcpu_reg32(const struct kvm_vcpu *vcpu, u8 reg_num) /* * Return the SPSR for the current mode of the virtual CPU. */ -unsigned long *vcpu_spsr32(const struct kvm_vcpu *vcpu) +static int vcpu_spsr32_mode(const struct kvm_vcpu *vcpu) { unsigned long mode = *vcpu_cpsr(vcpu) & COMPAT_PSR_MODE_MASK; switch (mode) { - case COMPAT_PSR_MODE_SVC: - mode = KVM_SPSR_SVC; - break; - case COMPAT_PSR_MODE_ABT: - mode = KVM_SPSR_ABT; - break; - case COMPAT_PSR_MODE_UND: - mode = KVM_SPSR_UND; - break; - case COMPAT_PSR_MODE_IRQ: - mode = KVM_SPSR_IRQ; - break; - case COMPAT_PSR_MODE_FIQ: - mode = KVM_SPSR_FIQ; - break; + case COMPAT_PSR_MODE_SVC: return KVM_SPSR_SVC; + case COMPAT_PSR_MODE_ABT: return KVM_SPSR_ABT; + case COMPAT_PSR_MODE_UND: return KVM_SPSR_UND; + case COMPAT_PSR_MODE_IRQ: return KVM_SPSR_IRQ; + case COMPAT_PSR_MODE_FIQ: return KVM_SPSR_FIQ; + default: BUG(); + } +} + +unsigned long vcpu_read_spsr32(const struct kvm_vcpu *vcpu) +{ + int spsr_idx = vcpu_spsr32_mode(vcpu); + + if (!vcpu->arch.sysregs_loaded_on_cpu) + return vcpu_gp_regs(vcpu)->spsr[spsr_idx]; + + switch (spsr_idx) { + case KVM_SPSR_SVC: + return read_sysreg_el1(spsr); + case KVM_SPSR_ABT: + return read_sysreg(spsr_abt); + case KVM_SPSR_UND: + return read_sysreg(spsr_und); + case KVM_SPSR_IRQ: + return read_sysreg(spsr_irq); + case KVM_SPSR_FIQ: + return read_sysreg(spsr_fiq); default: BUG(); } +} - return (unsigned long *)&vcpu_gp_regs(vcpu)->spsr[mode]; +void vcpu_write_spsr32(struct kvm_vcpu *vcpu, unsigned long v) +{ + int spsr_idx = vcpu_spsr32_mode(vcpu); + + if (!vcpu->arch.sysregs_loaded_on_cpu) + vcpu_gp_regs(vcpu)->spsr[spsr_idx] = v; + + switch (spsr_idx) { + case KVM_SPSR_SVC: + write_sysreg_el1(v, spsr); + case KVM_SPSR_ABT: + write_sysreg(v, spsr_abt); + case KVM_SPSR_UND: + write_sysreg(v, spsr_und); + case KVM_SPSR_IRQ: + write_sysreg(v, spsr_irq); + case KVM_SPSR_FIQ: + write_sysreg(v, spsr_fiq); + } } diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c index 8df651a8a36c..096ac84c9bbd 100644 --- a/arch/arm64/kvm/sys_regs.c +++ b/arch/arm64/kvm/sys_regs.c @@ -175,10 +175,10 @@ DECLARE_IMMEDIATE_SR(PMINTENSET_EL1); DECLARE_IMMEDIATE_SR(PMOVSSET_EL0); DECLARE_IMMEDIATE_SR(PMSWINC_EL0); DECLARE_IMMEDIATE_SR(PMUSERENR_EL0); -DECLARE_IMMEDIATE_SR(DACR32_EL2); -DECLARE_IMMEDIATE_SR(IFSR32_EL2); +DECLARE_DEFERRABLE_SR(DACR32_EL2, SYS_DACR32_EL2); +DECLARE_DEFERRABLE_SR(IFSR32_EL2, SYS_IFSR32_EL2); DECLARE_IMMEDIATE_SR(FPEXC32_EL2); -DECLARE_IMMEDIATE_SR(DBGVCR32_EL2); +DECLARE_DEFERRABLE_SR(DBGVCR32_EL2, SYS_DBGVCR32_EL2); static const struct sys_reg_accessor sys_reg_accessors[NR_SYS_REGS] = { [0 ... NR_SYS_REGS - 1] = {