From patchwork Tue Jan 16 18:53:05 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Jones X-Patchwork-Id: 10167937 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 971B8600CA for ; Tue, 16 Jan 2018 18:54:21 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 83BAC1FE82 for ; Tue, 16 Jan 2018 18:54:21 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 78A1C204FD; Tue, 16 Jan 2018 18:54:21 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=2.0 tests=BAYES_00,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 1A1CB1FE82 for ; Tue, 16 Jan 2018 18:54:21 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751531AbeAPSyT (ORCPT ); Tue, 16 Jan 2018 13:54:19 -0500 Received: from mx1.redhat.com ([209.132.183.28]:42696 "EHLO mx1.redhat.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751107AbeAPSyS (ORCPT ); Tue, 16 Jan 2018 13:54:18 -0500 Received: from smtp.corp.redhat.com (int-mx02.intmail.prod.int.phx2.redhat.com [10.5.11.12]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id B87C8A3282; Tue, 16 Jan 2018 18:54:18 +0000 (UTC) Received: from kamzik.brq.redhat.com (unknown [10.43.2.160]) by smtp.corp.redhat.com (Postfix) with ESMTP id D94E9609A6; Tue, 16 Jan 2018 18:54:04 +0000 (UTC) From: Andrew Jones To: kvm@vger.kernel.org Cc: pbonzini@redhat.com, rkrcmar@redhat.com, cdall@linaro.org, david@redhat.com, lvivier@redhat.com, thuth@redhat.com Subject: [PATCH kvm-unit-tests 04/11] arm/arm64: flush page table cache when installing entries Date: Tue, 16 Jan 2018 19:53:05 +0100 Message-Id: <20180116185312.7257-5-drjones@redhat.com> In-Reply-To: <20180116185312.7257-1-drjones@redhat.com> References: <20180116185312.7257-1-drjones@redhat.com> X-Scanned-By: MIMEDefang 2.79 on 10.5.11.12 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.39]); Tue, 16 Jan 2018 18:54:18 +0000 (UTC) Sender: kvm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This fixes the use of non-identity mapped page table entries for arm32 and AArch32 unit tests. Signed-off-by: Andrew Jones --- lib/arm/asm/mmu.h | 5 +++++ lib/arm/mmu.c | 17 +++++++++++++++-- lib/arm64/asm/mmu.h | 5 +++++ 3 files changed, 25 insertions(+), 2 deletions(-) diff --git a/lib/arm/asm/mmu.h b/lib/arm/asm/mmu.h index a31e19cd6652..915c2b07dead 100644 --- a/lib/arm/asm/mmu.h +++ b/lib/arm/asm/mmu.h @@ -37,6 +37,11 @@ static inline void flush_tlb_page(unsigned long vaddr) isb(); } +static inline void flush_dcache_addr(unsigned long vaddr) +{ + asm volatile("mcr p15, 0, %0, c7, c14, 1" :: "r" (vaddr)); +} + #include #endif /* __ASMARM_MMU_H_ */ diff --git a/lib/arm/mmu.c b/lib/arm/mmu.c index 9da3be38b339..548ec88277bc 100644 --- a/lib/arm/mmu.c +++ b/lib/arm/mmu.c @@ -73,6 +73,17 @@ void mmu_disable(void) asm_mmu_disable(); } +static void flush_entry(pgd_t *pgtable, uintptr_t vaddr) +{ + pgd_t *pgd = pgd_offset(pgtable, vaddr); + pmd_t *pmd = pmd_offset(pgd, vaddr); + + flush_dcache_addr((ulong)pgd); + flush_dcache_addr((ulong)pmd); + flush_dcache_addr((ulong)pte_offset(pmd, vaddr)); + flush_tlb_page(vaddr); +} + static pteval_t *get_pte(pgd_t *pgtable, uintptr_t vaddr) { pgd_t *pgd = pgd_offset(pgtable, vaddr); @@ -85,8 +96,9 @@ static pteval_t *get_pte(pgd_t *pgtable, uintptr_t vaddr) static pteval_t *install_pte(pgd_t *pgtable, uintptr_t vaddr, pteval_t pte) { pteval_t *p_pte = get_pte(pgtable, vaddr); + *p_pte = pte; - flush_tlb_page(vaddr); + flush_entry(pgtable, vaddr); return p_pte; } @@ -136,8 +148,9 @@ void mmu_set_range_sect(pgd_t *pgtable, uintptr_t virt_offset, pgd_val(*pgd) = paddr; pgd_val(*pgd) |= PMD_TYPE_SECT | PMD_SECT_AF | PMD_SECT_S; pgd_val(*pgd) |= pgprot_val(prot); + flush_dcache_addr((ulong)pgd); + flush_tlb_page(vaddr); } - flush_tlb_all(); } void *setup_mmu(phys_addr_t phys_end) diff --git a/lib/arm64/asm/mmu.h b/lib/arm64/asm/mmu.h index 9df99cc8871e..fa554b0c20ae 100644 --- a/lib/arm64/asm/mmu.h +++ b/lib/arm64/asm/mmu.h @@ -26,6 +26,11 @@ static inline void flush_tlb_page(unsigned long vaddr) dsb(ish); } +static inline void flush_dcache_addr(unsigned long vaddr) +{ + asm volatile("dc civac, %0" :: "r" (vaddr)); +} + #include #endif /* __ASMARM64_MMU_H_ */