| Message ID | 20180531165240.189036-1-jmattson@google.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
> On 31. May 2018, at 18:52, Jim Mattson <jmattson@google.com> wrote: > > From: Eric Northup <digitaleric@google.com> > > Return L2 cache and TLB information to guests. > They could have been set before, but the defaults that KVM returns will be > necessary for usermode that doesn't supply their own CPUID tables. > > Signed-off-by: Eric Northup <digitaleric@google.com> > Signed-off-by: Jim Mattson <jmattson@google.com> > --- > arch/x86/kvm/cpuid.c | 3 +++ > 1 file changed, 3 insertions(+) > > diff --git a/arch/x86/kvm/cpuid.c b/arch/x86/kvm/cpuid.c > index 72d8c492d71d4..5c604ac1093d5 100644 > --- a/arch/x86/kvm/cpuid.c > +++ b/arch/x86/kvm/cpuid.c > @@ -639,6 +639,9 @@ static inline int __do_cpuid_ent(struct kvm_cpuid_entry2 *entry, u32 function, > entry->edx &= boot_cpu_data.x86_power; > entry->eax = entry->ebx = entry->ecx = 0; > break; > + case 0x80000006: > + /* L2 cache and TLB: pass through host info. */ > + break; > case 0x80000008: { > unsigned g_phys_as = (entry->eax >> 16) & 0xff; > unsigned virt_as = max((entry->eax >> 8) & 0xff, 48U); > -- > 2.17.0.921.gf22659ad46-goog Reviewed-by: Filippo Sironi <sironi@amazon.de> Amazon Development Center Germany GmbH Berlin - Dresden - Aachen main office: Krausenstr. 38, 10117 Berlin Geschaeftsfuehrer: Dr. Ralf Herbrich, Christian Schlaeger Ust-ID: DE289237879 Eingetragen am Amtsgericht Charlottenburg HRB 149173 B
On Fri, 1 Jun 2018 at 00:55, Jim Mattson <jmattson@google.com> wrote: > > From: Eric Northup <digitaleric@google.com> > > Return L2 cache and TLB information to guests. > They could have been set before, but the defaults that KVM returns will be > necessary for usermode that doesn't supply their own CPUID tables. > > Signed-off-by: Eric Northup <digitaleric@google.com> > Signed-off-by: Jim Mattson <jmattson@google.com> > --- I boot a guest w/ -smp 8, sockets=1, cores=4, threads=2 -cpu host on a haswell client w/ and w/o the patch, what can be observed in the guest is the same. lscpu on the host: L1d cache: 32K L1i cache: 32K L2 cache: 256K L3 cache: 8192K lscpu in the guest: L1d cache: 32K L1i cache: 32K L2 cache: 4096K L3 cache: 16384K Regards, Wanpeng Li
2018-06-01 09:24+0800, Wanpeng Li: > On Fri, 1 Jun 2018 at 00:55, Jim Mattson <jmattson@google.com> wrote: > > > > From: Eric Northup <digitaleric@google.com> > > > > Return L2 cache and TLB information to guests. > > They could have been set before, but the defaults that KVM returns will be > > necessary for usermode that doesn't supply their own CPUID tables. > > > > Signed-off-by: Eric Northup <digitaleric@google.com> > > Signed-off-by: Jim Mattson <jmattson@google.com> > > --- > > I boot a guest w/ -smp 8, sockets=1, cores=4, threads=2 -cpu host on a > haswell client w/ and w/o the patch, what can be observed in the guest > is the same. That is because QEMU uses "host-cache-info" option for direct CPUID read if it wants to fill in the host values. Not sure why the host cpu model doesn't imply it. Other userspaces might rely on KVM as we already pass through other cache information, Reviewed-by: Radim Krčmář <rkrcmar@redhat.com>
diff --git a/arch/x86/kvm/cpuid.c b/arch/x86/kvm/cpuid.c index 72d8c492d71d4..5c604ac1093d5 100644 --- a/arch/x86/kvm/cpuid.c +++ b/arch/x86/kvm/cpuid.c @@ -639,6 +639,9 @@ static inline int __do_cpuid_ent(struct kvm_cpuid_entry2 *entry, u32 function, entry->edx &= boot_cpu_data.x86_power; entry->eax = entry->ebx = entry->ecx = 0; break; + case 0x80000006: + /* L2 cache and TLB: pass through host info. */ + break; case 0x80000008: { unsigned g_phys_as = (entry->eax >> 16) & 0xff; unsigned virt_as = max((entry->eax >> 8) & 0xff, 48U);