From patchwork Wed Jun 13 18:18:49 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marc Orr X-Patchwork-Id: 10462779 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 7CD9A6020F for ; Wed, 13 Jun 2018 18:19:32 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 6A99028FE5 for ; Wed, 13 Jun 2018 18:19:32 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 5EF7D28FEF; Wed, 13 Jun 2018 18:19:32 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.5 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI, USER_IN_DEF_DKIM_WL autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id C3FBB28FE5 for ; Wed, 13 Jun 2018 18:19:31 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S935369AbeFMST3 (ORCPT ); Wed, 13 Jun 2018 14:19:29 -0400 Received: from mail-yw0-f201.google.com ([209.85.161.201]:34320 "EHLO mail-yw0-f201.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S935206AbeFMST0 (ORCPT ); Wed, 13 Jun 2018 14:19:26 -0400 Received: by mail-yw0-f201.google.com with SMTP id w7-v6so2799067ywf.1 for ; Wed, 13 Jun 2018 11:19:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20161025; h=mime-version:date:message-id:subject:from:to:cc; bh=cIoCP7J7hwJqJQl+/JzYw19cXoYG9K6gqA2XaxyYtgo=; b=S8kgHF8d43Cq7cAqkE7pQr2K6L0aBOgl5OagvbjHn+R94PcRk3x4bPWwReMlKCwnSY MZSSoKIKXw29dQHaKYAlIQK3oi/GB8raoo+r/JCCXNVPQXMs1FVpzpotMCohd1wHh+0/ q2Yu0DRwNvc4qD23FhPF3QRprsnjLR4UntlZUfWmKzPB3wmO8kbdiplrJc3dCoU+3PcE tRCRbB1lvWzLrvE3lh6i2WNXc0Y0ceCGkP+Vfy4DFwlvWii7JwP1gMplzM7XFZa7cubM 7GRpbabc8sf6vI5MBdNH5UYPDmruFw8kIRcjn7pLBWs8nP9m87NV1AIf73OBel6LLbBj NhcA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:date:message-id:subject:from:to:cc; bh=cIoCP7J7hwJqJQl+/JzYw19cXoYG9K6gqA2XaxyYtgo=; b=mnJdG64aIQgmjT6TJvpZL6ecQQNL3n0786ZMkAyMOyv2N8KxIxCnFUY2tQFXHHxsxw 7h7pdAyrvBKLFgVjAVxsvmglReCiKZepmyd6CsesUkdor5JHm765JAc932V9CNvbPWkc ulemtZ5mNJnMsaJPKLF2theET1s0kdjqF3Hoz8B4ecxDOBoh+FjlyzvTL7QKbXwGrnqt hm4AqAbg2QI2+X68pEgWv7+kK23q+yCcraXgMGDNXDva9njxGP14kVkAWehbv91qZPTY /K39vUL0+fCMVJydWR4cr21169FFQElegwuHpDG4rCrSbpw2D945yZMq0f/26M3Ux9V9 8Y2w== X-Gm-Message-State: APt69E0IhRNb1FlTOpbfByru90PSK5l7kGDsYFFP1YGnAQ8W6CqaYAM+ sQI4T7KyJkNJwLFeKIiojehkEWcf1xB8JlRbif2Bcm3evMoCEcEaVVWJ7vSc4G0RoCvTzAHmBjK 66GdCqRvTe9Yy7ut2QnZXbDoLsVm1b2FJRZKQoXLw7tYqVmW92a7iXkLsUAbk X-Google-Smtp-Source: ADUXVKKGCHjMuvPzGy2sbIYBDsjzpkBu0y6fo93aNBq1sCsUERlBoj5r+7egkG4ByR6aabo2OIYoWdCAcQoT MIME-Version: 1.0 X-Received: by 2002:a81:1a42:: with SMTP id a63-v6mr1805014ywa.12.1528913965819; Wed, 13 Jun 2018 11:19:25 -0700 (PDT) Date: Wed, 13 Jun 2018 11:18:49 -0700 Message-Id: <20180613181849.98192-1-marcorr@google.com> X-Mailer: git-send-email 2.18.0.rc1.242.g61856ae69a-goog Subject: [PATCH] kvm: vmx: Nested VM-entry prereqs for event inj. From: Marc Orr To: kvm@vger.kernel.org, jmattson@google.com, pbonzini@redhat.com, rkrcmar@redhat.com Cc: Marc Orr Sender: kvm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This patch extends the checks done prior to a nested VM entry. Specifically, it extends the check_vmentry_prereqs function with checks for fields relevant to the VM-entry event injection information, as described in the Intel SDM, volume 3. This patch is motivated by a syzkaller bug, where a bad VM-entry interruption information field is generated in the VMCS02, which causes the nested VM launch to fail. Then, KVM fails to resume L1. While KVM should be improved to correctly resume L1 execution after a failed nested launch, this change is justified because the existing code to resume L1 is flaky/ad-hoc and the test coverage for resuming L1 is sparse. Signed-off-by: Marc Orr --- arch/x86/include/asm/vmx.h | 3 ++ arch/x86/kvm/vmx.c | 67 ++++++++++++++++++++++++++++++++++++++ arch/x86/kvm/x86.h | 10 ++++++ 3 files changed, 80 insertions(+) diff --git a/arch/x86/include/asm/vmx.h b/arch/x86/include/asm/vmx.h index 425e6b8b9547..6aa8499e1f62 100644 --- a/arch/x86/include/asm/vmx.h +++ b/arch/x86/include/asm/vmx.h @@ -114,6 +114,7 @@ #define VMX_MISC_PREEMPTION_TIMER_RATE_MASK 0x0000001f #define VMX_MISC_SAVE_EFER_LMA 0x00000020 #define VMX_MISC_ACTIVITY_HLT 0x00000040 +#define VMX_MISC_ZERO_LEN_INS 0x40000000 /* VMFUNC functions */ #define VMX_VMFUNC_EPTP_SWITCHING 0x00000001 @@ -351,11 +352,13 @@ enum vmcs_field { #define VECTORING_INFO_VALID_MASK INTR_INFO_VALID_MASK #define INTR_TYPE_EXT_INTR (0 << 8) /* external interrupt */ +#define INTR_TYPE_RESERVED (1 << 8) /* reserved */ #define INTR_TYPE_NMI_INTR (2 << 8) /* NMI */ #define INTR_TYPE_HARD_EXCEPTION (3 << 8) /* processor exception */ #define INTR_TYPE_SOFT_INTR (4 << 8) /* software interrupt */ #define INTR_TYPE_PRIV_SW_EXCEPTION (5 << 8) /* ICE breakpoint - undocumented */ #define INTR_TYPE_SOFT_EXCEPTION (6 << 8) /* software exception */ +#define INTR_TYPE_OTHER_EVENT (7 << 8) /* other event */ /* GUEST_INTERRUPTIBILITY_INFO flags. */ #define GUEST_INTR_STATE_STI 0x00000001 diff --git a/arch/x86/kvm/vmx.c b/arch/x86/kvm/vmx.c index 48989f78be60..8b2c3909ae69 100644 --- a/arch/x86/kvm/vmx.c +++ b/arch/x86/kvm/vmx.c @@ -1705,6 +1705,17 @@ static inline bool nested_cpu_has_vmwrite_any_field(struct kvm_vcpu *vcpu) MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS; } +static inline bool nested_cpu_has_zero_length_injection(struct kvm_vcpu *vcpu) +{ + return to_vmx(vcpu)->nested.msrs.misc_low & VMX_MISC_ZERO_LEN_INS; +} + +static inline bool nested_cpu_has_monitor_trap_flag(struct kvm_vcpu *vcpu) +{ + return to_vmx(vcpu)->nested.msrs.procbased_ctls_low & + CPU_BASED_MONITOR_TRAP_FLAG; +} + static inline bool nested_cpu_has(struct vmcs12 *vmcs12, u32 bit) { return vmcs12->cpu_based_vm_exec_control & bit; @@ -11612,6 +11623,62 @@ static int check_vmentry_prereqs(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12) !nested_cr3_valid(vcpu, vmcs12->host_cr3)) return VMXERR_ENTRY_INVALID_HOST_STATE_FIELD; + /* + * From the Intel SDM, volume 3: + * Fields relevant to VM-entry event injection must be set properly. + * These fields are the VM-entry interruption-information field, the + * VM-entry exception error code, and the VM-entry instruction length. + */ + if (vmcs12->vm_entry_intr_info_field & INTR_INFO_VALID_MASK) { + u32 intr_info = vmcs12->vm_entry_intr_info_field; + u8 nr = intr_info & INTR_INFO_VECTOR_MASK; + u32 intr_type = intr_info & INTR_INFO_INTR_TYPE_MASK; + bool has_error_code = intr_info & INTR_INFO_DELIVER_CODE_MASK; + bool should_have_error_code; + bool urg = nested_cpu_has2(vmcs12, + SECONDARY_EXEC_UNRESTRICTED_GUEST); + bool prot_mode = !urg || vmcs12->guest_cr0 & X86_CR0_PE; + + /* VM-entry interruption-info field: interruption type */ + if (intr_type == INTR_TYPE_RESERVED || + (intr_type == INTR_TYPE_OTHER_EVENT && + !nested_cpu_has_monitor_trap_flag(vcpu))) + return VMXERR_ENTRY_INVALID_CONTROL_FIELD; + + /* VM-entry interruption-info field: vector */ + if ((intr_type == INTR_TYPE_NMI_INTR && nr != NMI_VECTOR) || + (intr_type == INTR_TYPE_HARD_EXCEPTION && nr > 31) || + (intr_type == INTR_TYPE_OTHER_EVENT && nr != 0)) + return VMXERR_ENTRY_INVALID_CONTROL_FIELD; + + /* VM-entry interruption-info field: deliver error code */ + should_have_error_code = + intr_type == INTR_TYPE_HARD_EXCEPTION && + x86_exception_has_error_code(nr, prot_mode); + if (has_error_code != should_have_error_code) + return VMXERR_ENTRY_INVALID_CONTROL_FIELD; + + /* VM-entry interruption-info field: reserved bits */ + if (intr_info & INTR_INFO_RESVD_BITS_MASK) + return VMXERR_ENTRY_INVALID_CONTROL_FIELD; + + /* VM-entry exception error code */ + if (has_error_code && + vmcs12->vm_entry_exception_error_code & GENMASK(31, 15)) + return VMXERR_ENTRY_INVALID_CONTROL_FIELD; + + /* VM-entry instruction length */ + switch (intr_type) { + case INTR_TYPE_SOFT_EXCEPTION: + case INTR_TYPE_SOFT_INTR: + case INTR_TYPE_PRIV_SW_EXCEPTION: + if ((vmcs12->vm_entry_instruction_len > 15) || + (vmcs12->vm_entry_instruction_len == 0 && + !nested_cpu_has_zero_length_injection(vcpu))) + return VMXERR_ENTRY_INVALID_CONTROL_FIELD; + } + } + return 0; } diff --git a/arch/x86/kvm/x86.h b/arch/x86/kvm/x86.h index 331993c49dae..7a23a37c3bb1 100644 --- a/arch/x86/kvm/x86.h +++ b/arch/x86/kvm/x86.h @@ -110,6 +110,16 @@ static inline bool is_la57_mode(struct kvm_vcpu *vcpu) #endif } +static inline bool x86_exception_has_error_code(unsigned int nr, + bool protected_mode) +{ + static u32 exception_has_error_code = BIT(DF_VECTOR) | BIT(TS_VECTOR) | + BIT(NP_VECTOR) | BIT(SS_VECTOR) | BIT(GP_VECTOR) | + BIT(PF_VECTOR) | BIT(AC_VECTOR); + + return protected_mode && ((1U << nr) & exception_has_error_code); +} + static inline bool mmu_is_nested(struct kvm_vcpu *vcpu) { return vcpu->arch.walk_mmu == &vcpu->arch.nested_mmu;