From patchwork Thu Jun 28 13:52:21 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Janosch Frank X-Patchwork-Id: 10493999 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 393DC6022E for ; Thu, 28 Jun 2018 13:53:11 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 2271529980 for ; Thu, 28 Jun 2018 13:53:11 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 1644329A87; Thu, 28 Jun 2018 13:53:11 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.9 required=2.0 tests=BAYES_00, MAILING_LIST_MULTI, RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 9D17829980 for ; Thu, 28 Jun 2018 13:53:10 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S966160AbeF1NxI (ORCPT ); Thu, 28 Jun 2018 09:53:08 -0400 Received: from mx0a-001b2d01.pphosted.com ([148.163.156.1]:54240 "EHLO mx0a-001b2d01.pphosted.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S965482AbeF1NxH (ORCPT ); Thu, 28 Jun 2018 09:53:07 -0400 Received: from pps.filterd (m0098399.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.16.0.22/8.16.0.22) with SMTP id w5SDoCHi093871 for ; Thu, 28 Jun 2018 09:53:06 -0400 Received: from e06smtp04.uk.ibm.com (e06smtp04.uk.ibm.com [195.75.94.100]) by mx0a-001b2d01.pphosted.com with ESMTP id 2jvwpq2f37-1 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=NOT) for ; Thu, 28 Jun 2018 09:53:06 -0400 Received: from localhost by e06smtp04.uk.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! 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Violators will be prosecuted; (version=TLSv1/SSLv3 cipher=AES256-GCM-SHA384 bits=256/256) Thu, 28 Jun 2018 14:53:01 +0100 Received: from d06av24.portsmouth.uk.ibm.com (mk.ibm.com [9.149.105.60]) by b06cxnps3075.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id w5SDr0Gm18088096 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=FAIL); Thu, 28 Jun 2018 13:53:00 GMT Received: from d06av24.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id F375742042; Thu, 28 Jun 2018 14:52:50 +0100 (BST) Received: from d06av24.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 73E9A4203F; Thu, 28 Jun 2018 14:52:50 +0100 (BST) Received: from s38lp20.boeblingen.de.ibm.com (unknown [9.145.1.23]) by d06av24.portsmouth.uk.ibm.com (Postfix) with ESMTP; Thu, 28 Jun 2018 14:52:50 +0100 (BST) From: Janosch Frank To: david@redhat.com Cc: kvm@vger.kernel.org, thuth@redhat.com Subject: [kvm-unit-tests PATCH v3] s390x: Catch all exceptions Date: Thu, 28 Jun 2018 14:52:21 +0100 X-Mailer: git-send-email 2.14.3 X-TM-AS-GCONF: 00 x-cbid: 18062813-0016-0000-0000-000001E12807 X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 18062813-0017-0000-0000-000032356DD7 Message-Id: <20180628135221.72818-1-frankja@linux.ibm.com> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:, , definitions=2018-06-28_07:, , signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 suspectscore=1 phishscore=0 bulkscore=0 spamscore=0 clxscore=1015 lowpriorityscore=0 mlxscore=0 impostorscore=0 mlxlogscore=534 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1806210000 definitions=main-1806280158 Sender: kvm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Right now we only catch the exceptions that we really expect to receive. Let's at least catch all of them and abort if any of the unexpected ones fell on our foot. Signed-off-by: Janosch Frank Reviewed-by: Thomas Huth --- lib/s390x/asm/interrupt.h | 4 ++++ lib/s390x/interrupt.c | 24 ++++++++++++++++++++ s390x/cstart64.S | 58 ++++++++++++++++++++++++++++++++++++++++++++--- 3 files changed, 83 insertions(+), 3 deletions(-) diff --git a/lib/s390x/asm/interrupt.h b/lib/s390x/asm/interrupt.h index 3ccc8e3..b3abd63 100644 --- a/lib/s390x/asm/interrupt.h +++ b/lib/s390x/asm/interrupt.h @@ -12,6 +12,10 @@ #include void handle_pgm_int(void); +void handle_ext_int(void); +void handle_mcck_int(void); +void handle_io_int(void); +void handle_svc_int(void); void expect_pgm_int(void); uint16_t clear_pgm_int(void); void check_pgm_int_code(uint16_t code); diff --git a/lib/s390x/interrupt.c b/lib/s390x/interrupt.c index bc44e3a..848d5f2 100644 --- a/lib/s390x/interrupt.c +++ b/lib/s390x/interrupt.c @@ -104,3 +104,27 @@ void handle_pgm_int(void) pgm_int_expected = false; fixup_pgm_int(); } + +void handle_ext_int(void) +{ + report_abort("Unexpected external call interrupt: at %#lx", + lc->ext_old_psw.addr); +} + +void handle_mcck_int(void) +{ + report_abort("Unexpected machine check interrupt: at %#lx", + lc->mcck_old_psw.addr); +} + +void handle_io_int(void) +{ + report_abort("Unexpected io interrupt: at %#lx", + lc->io_old_psw.addr); +} + +void handle_svc_int(void) +{ + report_abort("Unexpected service call interrupt: at %#lx", + lc->svc_old_psw.addr); +} diff --git a/s390x/cstart64.S b/s390x/cstart64.S index 9a26ed3..2f02d4d 100644 --- a/s390x/cstart64.S +++ b/s390x/cstart64.S @@ -26,6 +26,18 @@ init_psw_cont: /* setup pgm interrupt handler */ larl %r1, pgm_int_psw mvc GEN_LC_PGM_NEW_PSW(16), 0(%r1) + /* setup ext interrupt handler */ + larl %r1, ext_int_psw + mvc GEN_LC_EXT_NEW_PSW(16), 0(%r1) + /* setup mcck interrupt handler */ + larl %r1, mcck_int_psw + mvc GEN_LC_MCCK_NEW_PSW(16), 0(%r1) + /* setup io interrupt handler */ + larl %r1, ext_int_psw + mvc GEN_LC_IO_NEW_PSW(16), 0(%r1) + /* setup svc interrupt handler */ + larl %r1, mcck_int_psw + mvc GEN_LC_SVC_NEW_PSW(16), 0(%r1) /* setup cr0, enabling e.g. AFP-register control */ larl %r1, initital_cr0 lctlg %c0, %c0, 0(%r1) @@ -42,7 +54,7 @@ init_psw_cont: /* call exit() */ j exit -pgm_int: + .macro SAVE_REGS /* save grs 0-15 */ stmg %r0, %r15, GEN_LC_SW_INT_GRS /* save fprs 0-15 + fpc */ @@ -64,8 +76,9 @@ pgm_int: std %f14, 112(%r1) std %f15, 120(%r1) stfpc GEN_LC_SW_INT_FPC - /* call our c handler */ - brasl %r14, handle_pgm_int + .endm + + .macro RESTORE_REGS /* restore fprs 0-15 + fpc */ larl %r1, GEN_LC_SW_INT_FPRS ld %f0, 0(%r1) @@ -87,13 +100,52 @@ pgm_int: lfpc GEN_LC_SW_INT_FPC /* restore grs 0-15 */ lmg %r0, %r15, GEN_LC_SW_INT_GRS + .endm + +.section .text +pgm_int: + SAVE_REGS + brasl %r14, handle_pgm_int + RESTORE_REGS lpswe GEN_LC_PGM_OLD_PSW +ext_int: + SAVE_REGS + brasl %r14, handle_ext_int + RESTORE_REGS + lpswe GEN_LC_EXT_OLD_PSW + +mcck_int: + SAVE_REGS + brasl %r14, handle_mcck_int + RESTORE_REGS + lpswe GEN_LC_MCCK_OLD_PSW + +io_int: + SAVE_REGS + brasl %r14, handle_io_int + RESTORE_REGS + lpswe GEN_LC_IO_OLD_PSW + +svc_int: + SAVE_REGS + brasl %r14, handle_svc_int + RESTORE_REGS + lpswe GEN_LC_SVC_OLD_PSW + .align 8 initital_psw: .quad 0x0000000180000000, init_psw_cont pgm_int_psw: .quad 0x0000000180000000, pgm_int +ext_int_psw: + .quad 0x0000000180000000, ext_int +mcck_int_psw: + .quad 0x0000000180000000, mcck_int +io_int_psw: + .quad 0x0000000180000000, io_int +svc_int_psw: + .quad 0x0000000180000000, svc_int initital_cr0: /* enable AFP-register control, so FP regs (+BFP instr) can be used */ .quad 0x0000000000040000