| Message ID | 20180718202651.19802-2-sean.j.christopherson@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On 07/18/2018 01:26 PM, Sean Christopherson wrote: > test_tpr_threshold() could theoretically leave CPU_TPR_SHADOW set in > its early return path when none of the secondary controls needed for > the remaining tests are supported. > > Fix the prefix for the TPR-enabled, sec_exec-disabled case. > > Signed-off-by: Sean Christopherson <sean.j.christopherson@intel.com> > --- > x86/vmx_tests.c | 6 ++++-- > 1 file changed, 4 insertions(+), 2 deletions(-) > > diff --git a/x86/vmx_tests.c b/x86/vmx_tests.c > index 6c73041..ab6e089 100644 > --- a/x86/vmx_tests.c > +++ b/x86/vmx_tests.c > @@ -4085,13 +4085,15 @@ static void test_tpr_threshold(void) > test_tpr_threshold_values(); > report_prefix_pop(); > vmcs_write(CPU_EXEC_CTRL0, vmcs_read(CPU_EXEC_CTRL0) | CPU_TPR_SHADOW); > - report_prefix_pushf("Use TPR shadow enabled"); > + report_prefix_pushf("Use TPR shadow enabled, secondary controls disabled"); > test_tpr_threshold_values(); > report_prefix_pop(); > > if (!((ctrl_cpu_rev[0].clr & CPU_SECONDARY) && > - (ctrl_cpu_rev[1].clr & (CPU_VINTD | CPU_VIRT_APIC_ACCESSES)))) > + (ctrl_cpu_rev[1].clr & (CPU_VINTD | CPU_VIRT_APIC_ACCESSES)))) { > + vmcs_write(CPU_EXEC_CTRL0, primary); > return; > + } > > u32 secondary = vmcs_read(CPU_EXEC_CTRL1); > Reviewed-by: Krish Sadhukhan <krish.sadhukhan@oracle.com>
diff --git a/x86/vmx_tests.c b/x86/vmx_tests.c index 6c73041..ab6e089 100644 --- a/x86/vmx_tests.c +++ b/x86/vmx_tests.c @@ -4085,13 +4085,15 @@ static void test_tpr_threshold(void) test_tpr_threshold_values(); report_prefix_pop(); vmcs_write(CPU_EXEC_CTRL0, vmcs_read(CPU_EXEC_CTRL0) | CPU_TPR_SHADOW); - report_prefix_pushf("Use TPR shadow enabled"); + report_prefix_pushf("Use TPR shadow enabled, secondary controls disabled"); test_tpr_threshold_values(); report_prefix_pop(); if (!((ctrl_cpu_rev[0].clr & CPU_SECONDARY) && - (ctrl_cpu_rev[1].clr & (CPU_VINTD | CPU_VIRT_APIC_ACCESSES)))) + (ctrl_cpu_rev[1].clr & (CPU_VINTD | CPU_VIRT_APIC_ACCESSES)))) { + vmcs_write(CPU_EXEC_CTRL0, primary); return; + } u32 secondary = vmcs_read(CPU_EXEC_CTRL1);
test_tpr_threshold() could theoretically leave CPU_TPR_SHADOW set in its early return path when none of the secondary controls needed for the remaining tests are supported. Fix the prefix for the TPR-enabled, sec_exec-disabled case. Signed-off-by: Sean Christopherson <sean.j.christopherson@intel.com> --- x86/vmx_tests.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-)