diff mbox series

[v5,02/18] kvm: arm/arm64: Remove spurious WARN_ON

Message ID	20180917104144.19188-3-suzuki.poulose@arm.com (mailing list archive)
State	New, archived
Headers	show Return-Path: <kvm-owner@kernel.org> From: Suzuki K Poulose <suzuki.poulose@arm.com> To: linux-arm-kernel@lists.infradead.org Cc: kvmarm@lists.cs.columbia.edu, kvm@vger.kernel.org, marc.zyngier@arm.com, cdall@kernel.org, eric.auger@redhat.com, pbonzini@redhat.com, rkrcmar@redhat.com, will.deacon@arm.com, catalin.marinas@arm.com, james.morse@arm.com, dave.martin@arm.com, julien.grall@arm.com, linux-kernel@vger.kernel.org, suzuki.poulose@arm.com Subject: [PATCH v5 02/18] kvm: arm/arm64: Remove spurious WARN_ON Date: Mon, 17 Sep 2018 11:41:24 +0100 Message-Id: <20180917104144.19188-3-suzuki.poulose@arm.com> In-Reply-To: <20180917104144.19188-1-suzuki.poulose@arm.com> References: <20180917104144.19188-1-suzuki.poulose@arm.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Sender: kvm-owner@vger.kernel.org Precedence: bulk
Series	kvm: arm64: Dynamic IPA and 52bit IPA \| expand [v5,00/18] kvm: arm64: Dynamic IPA and 52bit IPA [v5,01/18] kvm: arm/arm64: Fix stage2_flush_memslot for 4 level page table [v5,02/18] kvm: arm/arm64: Remove spurious WARN_ON [v5,03/18] kvm: arm64: Add helper for loading the stage2 setting for a VM [v5,04/18] arm64: Add a helper for PARange to physical shift conversion [v5,05/18] kvm: arm64: Clean up VTCR_EL2 initialisation [v5,06/18] kvm: arm/arm64: Allow arch specific configurations for VM [v5,07/18] kvm: arm64: Configure VTCR_EL2 per VM [v5,08/18] kvm: arm/arm64: Prepare for VM specific stage2 translations [v5,09/18] kvm: arm64: Prepare for dynamic stage2 page table layout [v5,10/18] kvm: arm64: Make stage2 page table layout dynamic [v5,11/18] kvm: arm64: Dynamic configuration of VTTBR mask [v5,12/18] kvm: arm64: Configure VTCR_EL2.SL0 per VM [v5,13/18] kvm: arm64: Switch to per VM IPA limit [v5,14/18] vgic: Add support for 52bit guest physical address [v5,15/18] kvm: arm64: Add 52bit support for PAR to HPFAR conversoin [v5,16/18] kvm: arm64: Set a limit on the IPA size [v5,17/18] kvm: arm64: Limit the minimum number of page table levels [v5,18/18] kvm: arm64: Allow tuning the physical address size for VM [kvmtool,v5,19/18] kvmtool: Allow backends to run checks on the KVM device fd [kvmtool,v5,20/18] kvmtool: arm64: Add support for guest physical address size [kvmtool,v5,21/18] kvmtool: arm64: Switch memory layout [kvmtool,v5,22/18] kvmtool: arm: Add support for creating VM with PA size

Commit Message

Suzuki K Poulose Sept. 17, 2018, 10:41 a.m. UTC

On a 4-level page table pgd entry can be empty, unlike a 3-level
page table. Remove the spurious WARN_ON() in stage_get_pud().

Acked-by: Christoffer Dall <cdall@kernel.org>
Acked-by: Marc Zyngier <marc.zyngier@arm.com>
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
---
 virt/kvm/arm/mmu.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff mbox series

Patch

diff --git a/virt/kvm/arm/mmu.c b/virt/kvm/arm/mmu.c
index ee7ce8fa4a12..4a285d760ce0 100644
--- a/virt/kvm/arm/mmu.c
+++ b/virt/kvm/arm/mmu.c
@@ -1005,7 +1005,7 @@  static pud_t *stage2_get_pud(struct kvm *kvm, struct kvm_mmu_memory_cache *cache
 	pud_t *pud;
 
 	pgd = kvm->arch.pgd + stage2_pgd_index(addr);
-	if (WARN_ON(stage2_pgd_none(*pgd))) {
+	if (stage2_pgd_none(*pgd)) {
 		if (!cache)
 			return NULL;
 		pud = mmu_memory_cache_alloc(cache);