From patchwork Tue Oct 16 21:29:24 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jim Mattson X-Patchwork-Id: 10644229 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 8478B109C for ; Tue, 16 Oct 2018 21:29:55 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 757392A9D3 for ; Tue, 16 Oct 2018 21:29:55 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 69F132A9DF; Tue, 16 Oct 2018 21:29:55 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.5 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI, USER_IN_DEF_DKIM_WL autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id EEB272A9D3 for ; Tue, 16 Oct 2018 21:29:54 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727059AbeJQFWL (ORCPT ); Wed, 17 Oct 2018 01:22:11 -0400 Received: from mail-pg1-f202.google.com ([209.85.215.202]:33481 "EHLO mail-pg1-f202.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727050AbeJQFWL (ORCPT ); Wed, 17 Oct 2018 01:22:11 -0400 Received: by mail-pg1-f202.google.com with SMTP id t3-v6so18382902pgp.0 for ; Tue, 16 Oct 2018 14:29:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20161025; h=date:in-reply-to:message-id:mime-version:references:subject:from:to :cc; bh=zVGPdWwjQpYEjZ9wVk1C68kQJiUOgREi3pvqdfVIpqU=; b=p5pFY0RB9uaLeje2ws2vXLI3OfwS7j33XTBUkEUYzTRy/PTipLeyrL6fWWeibXAE2h Ev2wSqzlqC4QIL1xLSfCRvx4gs4wQGZgKzrPGTyM1ByIn5oEMiBmhL4pW615niClxaLa qIVWaIRtG/j2NjTIJ/O8NQxyLsBNweB6g4avECU5croqb4vGj3FFafvnEIs0GbEcNfzL NwyaY5l5eiloXuM3A5Yg2V6JmQ1qPpW873Q0CpoLnu5ob73XIckl9Ofkwu6YPeoWUMef VzSgPkTbkXp6zCQaZtYOa761onm1iMdZo1kAFSzo/UadtBvpd0UUJ5bTf+bS52AxR0ya RaxQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:in-reply-to:message-id:mime-version :references:subject:from:to:cc; bh=zVGPdWwjQpYEjZ9wVk1C68kQJiUOgREi3pvqdfVIpqU=; b=qfC9aiJpt3bDTBlC+uLPEaiep5jQbx/Vj/fxT6MZH7OGKIdCVjlI7ikahcevig3+od T/3KY7zPoHwo1NybprXQ5ijRlvHvIcyWR1i3iZG9TLIUQei9Mu2E6UUea4In3Tfsoahs PdmKeqVsSvo4afaXDjxymUeCF05sRIbYl2kPW3o2pgiqrZ9FnVxxXxZQ6zWUGQii99S2 9JoG5lkPYoO4YSIgaIR5LY+OmsFrYy8mPtYMouHxFwfRoaEti+EOMWv4JGB5fiPFgWkU Ae4ZbhaDAT56LkuHUe4m8MPi2lXyanwPivEtq3J/zZ4/WE/thDLn+y6dot3MTDwKS+lv 8vcw== X-Gm-Message-State: ABuFfoiVfc+sBiOiVwPIp/z3EA+2P5w6aLoV9MW2FHgEwrc7ckCQCbfm 9eFBibW2NofqyrE9ZjcmZ/gJ0esbT7fowSLN6vbTOQc9R+GjgWhiDYrjPb5bsCZqwL6dKfYoTTX Zi2vuYW6hQ0taMXH86Zm4kfwGgrUSExk92cKq2bO6w99MTD2wYSGBK0eu92UwoJg= X-Google-Smtp-Source: ACcGV60hP2B7+Ibvvs+WxcdBzWgIj4leJW3ToaI/6lZV1BLM0JVKrUV4+3ix50ukCYLohcY2SLwOl9afi6FXgA== X-Received: by 2002:a62:939b:: with SMTP id r27-v6mr11611827pfk.3.1539725392627; Tue, 16 Oct 2018 14:29:52 -0700 (PDT) Date: Tue, 16 Oct 2018 14:29:24 -0700 In-Reply-To: <20181016212924.130307-1-jmattson@google.com> Message-Id: <20181016212924.130307-7-jmattson@google.com> Mime-Version: 1.0 References: <20181016212924.130307-1-jmattson@google.com> X-Mailer: git-send-email 2.19.1.331.ge82ca0e54c-goog Subject: [PATCH v2 7/7] kvm: x86: Introduce KVM_CAP_EXCEPTION_PAYLOAD From: Jim Mattson To: kvm@vger.kernel.org Cc: Peter Shier , Liran Alon , Paolo Bonzini , Jim Mattson Sender: kvm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This is a per-VM capability which can be enabled by userspace so that the faulting linear address will be included with the information about a pending #PF in L2, and the "new DR6 bits" will be included with the information about a pending #DB in L2. With this capability enabled, the L1 hypervisor can now intercept #PF before CR2 is modified. Under VMX, the L1 hypervisor can now intercept #DB before DR6 and DR7 are modified. When userspace has enabled KVM_CAP_EXCEPTION_PAYLOAD, it should generally provide an appropriate payload when injecting a #PF or #DB exception via KVM_SET_VCPU_EVENTS. However, to support restoring old checkpoints, this payload is not required. Note that bit 16 of the "new DR6 bits" is set to indicate that a debug exception (#DB) or a breakpoint exception (#BP) occurred inside an RTM region while advanced debugging of RTM transactional regions was enabled. This is the reverse of DR6.RTM, which is cleared in this scenario. This capability also enables exception.pending in struct kvm_vcpu_events, which allows userspace to distinguish between pending and injected exceptions. Reported-by: Jim Mattson Suggested-by: Paolo Bonzini Signed-off-by: Jim Mattson --- Documentation/virtual/kvm/api.txt | 25 +++++++++++++++++++++++++ arch/x86/kvm/x86.c | 5 +++++ include/uapi/linux/kvm.h | 1 + 3 files changed, 31 insertions(+) diff --git a/Documentation/virtual/kvm/api.txt b/Documentation/virtual/kvm/api.txt index 065093f5be92..cd22478739d8 100644 --- a/Documentation/virtual/kvm/api.txt +++ b/Documentation/virtual/kvm/api.txt @@ -4544,6 +4544,31 @@ With this capability, a guest may read the MSR_PLATFORM_INFO MSR. Otherwise, a #GP would be raised when the guest tries to access. Currently, this capability does not enable write permissions of this MSR for the guest. +7.15 KVM_CAP_EXCEPTION_PAYLOAD + +Architectures: x86 +Parameters: args[0] whether feature should be enabled or not + +With this capability enabled, CR2 will not be modified prior to the +emulated VM-exit when L1 intercepts a #PF exception that occurs in +L2. Similarly, for kvm-intel only, DR6 will not be modified prior to +the emulated VM-exit when L1 intercepts a #DB exception that occurs in +L2. As a result, when KVM_GET_VCPU_EVENTS reports a pending #PF (or +#DB) exception for L2, exception.has_payload will be set and the +faulting address (or the new DR6 bits*) will be reported in the +exception_payload field. Similarly, when userspace injects a #PF (or +#DB) into L2 using KVM_SET_VCPU_EVENTS, it is expected to set +exception.has_payload and to put the faulting address (or the new DR6 +bits*) in the exception_payload field. + +This capability also enables exception.pending in struct +kvm_vcpu_events, which allows userspace to distinguish between pending +and injected exceptions. + + +* For the new DR6 bits, note that bit 16 is set iff the #DB exception + will clear DR6.RTM. + 8. Other capabilities. ---------------------- diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c index d68c34a74590..abe5c29c4323 100644 --- a/arch/x86/kvm/x86.c +++ b/arch/x86/kvm/x86.c @@ -3013,6 +3013,7 @@ int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext) case KVM_CAP_IMMEDIATE_EXIT: case KVM_CAP_GET_MSR_FEATURES: case KVM_CAP_MSR_PLATFORM_INFO: + case KVM_CAP_EXCEPTION_PAYLOAD: r = 1; break; case KVM_CAP_SYNC_REGS: @@ -4477,6 +4478,10 @@ static int kvm_vm_ioctl_enable_cap(struct kvm *kvm, kvm->arch.guest_can_read_msr_platform_info = cap->args[0]; r = 0; break; + case KVM_CAP_EXCEPTION_PAYLOAD: + kvm->arch.exception_payload_enabled = cap->args[0]; + r = 0; + break; default: r = -EINVAL; break; diff --git a/include/uapi/linux/kvm.h b/include/uapi/linux/kvm.h index 251be353f950..531da3d1fd55 100644 --- a/include/uapi/linux/kvm.h +++ b/include/uapi/linux/kvm.h @@ -953,6 +953,7 @@ struct kvm_ppc_resize_hpt { #define KVM_CAP_NESTED_STATE 157 #define KVM_CAP_ARM_INJECT_SERROR_ESR 158 #define KVM_CAP_MSR_PLATFORM_INFO 159 +#define KVM_CAP_EXCEPTION_PAYLOAD 160 #ifdef KVM_CAP_IRQ_ROUTING