diff mbox series

x86: Wait for self IPI

Message ID 20190415230327.23949-1-nadav.amit@gmail.com (mailing list archive)
State New, archived
Headers show
Series x86: Wait for self IPI | expand

Commit Message

Nadav Amit April 15, 2019, 11:03 p.m. UTC 
From: Nadav Amit <nadav.amit@gmail.com>

There is no architectural requirement that self-IPI would be received on
the next instruction after it is generated. Make the test more robust by
not requiring it, and instead wait for some time or until it is
received.

Signed-off-by: Nadav Amit <nadav.amit@gmail.com>
---
 x86/apic.c | 7 ++++++-
 1 file changed, 6 insertions(+), 1 deletion(-)

Comments

Nadav Amit April 15, 2019, 11:04 p.m. UTC | #1 
> On Apr 15, 2019, at 4:03 PM, nadav.amit@gmail.com wrote:
> 
> From: Nadav Amit <nadav.amit@gmail.com>
> 
> There is no architectural requirement that self-IPI would be received on
> the next instruction after it is generated. Make the test more robust by
> not requiring it, and instead wait for some time or until it is
> received.
> 
> Signed-off-by: Nadav Amit <nadav.amit@gmail.com>
> ---
> x86/apic.c | 7 ++++++-
> 1 file changed, 6 insertions(+), 1 deletion(-)
> 
> diff --git a/x86/apic.c b/x86/apic.c
> index 0849f87..de5990c 100644
> --- a/x86/apic.c
> +++ b/x86/apic.c
> @@ -255,13 +255,18 @@ static void self_ipi_isr(isr_regs_t *regs)
> 
> static void test_self_ipi(void)
> {
> +    u64 start = rdtsc();
>     int vec = 0xf1;
> 
>     handle_irq(vec, self_ipi_isr);
>     irq_enable();
>     apic_icr_write(APIC_DEST_SELF | APIC_DEST_PHYSICAL | APIC_DM_FIXED | vec,
>                    0);
> -    asm volatile ("nop");
> +
> +    do {
> +        pause();
> +    } while (rdtsc() - start < 1000000000 && ipi_count == 0);
> +
>     report("self ipi", ipi_count == 1);
> }
> 
> -- 
> 2.17.1

This is of course a KVM-unit-tests patch.
Paolo Bonzini April 16, 2019, 3:24 p.m. UTC | #2 
On 16/04/19 01:04, Nadav Amit wrote:
>> On Apr 15, 2019, at 4:03 PM, nadav.amit@gmail.com wrote:
>>
>> From: Nadav Amit <nadav.amit@gmail.com>
>>
>> There is no architectural requirement that self-IPI would be received on
>> the next instruction after it is generated. Make the test more robust by
>> not requiring it, and instead wait for some time or until it is
>> received.
>>
>> Signed-off-by: Nadav Amit <nadav.amit@gmail.com>
>> ---
>> x86/apic.c | 7 ++++++-
>> 1 file changed, 6 insertions(+), 1 deletion(-)
>>
>> diff --git a/x86/apic.c b/x86/apic.c
>> index 0849f87..de5990c 100644
>> --- a/x86/apic.c
>> +++ b/x86/apic.c
>> @@ -255,13 +255,18 @@ static void self_ipi_isr(isr_regs_t *regs)
>>
>> static void test_self_ipi(void)
>> {
>> +    u64 start = rdtsc();
>>     int vec = 0xf1;
>>
>>     handle_irq(vec, self_ipi_isr);
>>     irq_enable();
>>     apic_icr_write(APIC_DEST_SELF | APIC_DEST_PHYSICAL | APIC_DM_FIXED | vec,
>>                    0);
>> -    asm volatile ("nop");
>> +
>> +    do {
>> +        pause();
>> +    } while (rdtsc() - start < 1000000000 && ipi_count == 0);
>> +
>>     report("self ipi", ipi_count == 1);
>> }
>>
>> -- 
>> 2.17.1
> 
> This is of course a KVM-unit-tests patch.
> 

which I've queued, thanks.

Paolo
diff mbox series

Patch

diff --git a/x86/apic.c b/x86/apic.c
index 0849f87..de5990c 100644
--- a/x86/apic.c
+++ b/x86/apic.c
@@ -255,13 +255,18 @@  static void self_ipi_isr(isr_regs_t *regs)
 
 static void test_self_ipi(void)
 {
+    u64 start = rdtsc();
     int vec = 0xf1;
 
     handle_irq(vec, self_ipi_isr);
     irq_enable();
     apic_icr_write(APIC_DEST_SELF | APIC_DEST_PHYSICAL | APIC_DM_FIXED | vec,
                    0);
-    asm volatile ("nop");
+
+    do {
+        pause();
+    } while (rdtsc() - start < 1000000000 && ipi_count == 0);
+
     report("self ipi", ipi_count == 1);
 }