| Message ID | 20190621093843.220980-49-marc.zyngier@arm.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | KVM: arm64: ARMv8.3 Nested Virtualization support | expand |
On 6/21/19 10:38 AM, Marc Zyngier wrote: > In order for vgic_v3_load_nested to be able to observe which > which timer interrupts have the HW bit set for the current s/which which/which > context, the timers must have been loaded in the new mode > and the right timer mapped to their corresponding HW IRQs. > > At the moment, we load the GIC first, meaning that timer > interrupts injected to an L2 guest will never have the HW > HW bit set (we see the old configuration). s/HW HW/HW > Swapping the two loads solves this particular problem. > > Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> > --- > virt/kvm/arm/arm.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/virt/kvm/arm/arm.c b/virt/kvm/arm/arm.c > index e8b584b79847..ca10a11e044e 100644 > --- a/virt/kvm/arm/arm.c > +++ b/virt/kvm/arm/arm.c > @@ -361,8 +361,8 @@ void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu) > vcpu->arch.host_cpu_context = &cpu_data->host_ctxt; > > kvm_arm_set_running_vcpu(vcpu); > - kvm_vgic_load(vcpu); > kvm_timer_vcpu_load(vcpu); > + kvm_vgic_load(vcpu); > kvm_vcpu_load_sysregs(vcpu); > kvm_arch_vcpu_load_fp(vcpu); > kvm_vcpu_pmu_restore_guest(vcpu);
diff --git a/virt/kvm/arm/arm.c b/virt/kvm/arm/arm.c index e8b584b79847..ca10a11e044e 100644 --- a/virt/kvm/arm/arm.c +++ b/virt/kvm/arm/arm.c @@ -361,8 +361,8 @@ void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu) vcpu->arch.host_cpu_context = &cpu_data->host_ctxt; kvm_arm_set_running_vcpu(vcpu); - kvm_vgic_load(vcpu); kvm_timer_vcpu_load(vcpu); + kvm_vgic_load(vcpu); kvm_vcpu_load_sysregs(vcpu); kvm_arch_vcpu_load_fp(vcpu); kvm_vcpu_pmu_restore_guest(vcpu);
In order for vgic_v3_load_nested to be able to observe which which timer interrupts have the HW bit set for the current context, the timers must have been loaded in the new mode and the right timer mapped to their corresponding HW IRQs. At the moment, we load the GIC first, meaning that timer interrupts injected to an L2 guest will never have the HW HW bit set (we see the old configuration). Swapping the two loads solves this particular problem. Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> --- virt/kvm/arm/arm.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)