| Message ID | 20190724090437.49952-3-xiexiangyou@huawei.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | KVM: arm/arm64: Optimize lpi translation cache performance | expand |
On 24/07/2019 10:04, Xiangyou Xie wrote: > It is not necessary to invalidate the lpi translation cache when the > virtual machine executes the movi instruction to adjust the affinity of > the interrupt. Irqbalance will adjust the interrupt affinity in a short > period of time to achieve the purpose of interrupting load balancing, > but this does not affect the contents of the lpi translation cache. What does irqbalance have to do with it? We're dealing with the GIC architecture here, not with userspace. If the guest issues a MOVI command to a RD where GICR_CTLR.EnableLPI is 0, and that we use an existing cached translation, we are going to make the interrupt pending for that RD. This is direct violation of the architecture, which says: "LPI support is disabled. Any doorbell interrupt generated as a result of a write to a virtual LPI register must be discarded, and any ITS translation requests or commands involving LPIs in this Redistributor are ignored." So the interrupt cannot be made pending. No IFs, no BUTs. If you really want to optimize it, check that the target RD is actually enabled and only invalidate in this particular case. Your guest would have to have a rate of MOVI that is comparable to that of the interrupts for it to show on any radar though... Thanks, M.
diff --git a/virt/kvm/arm/vgic/vgic-its.c b/virt/kvm/arm/vgic/vgic-its.c index 792d90b..66e93ab 100644 --- a/virt/kvm/arm/vgic/vgic-its.c +++ b/virt/kvm/arm/vgic/vgic-its.c @@ -907,8 +907,6 @@ static int vgic_its_cmd_handle_movi(struct kvm *kvm, struct vgic_its *its, ite->collection = collection; vcpu = kvm_get_vcpu(kvm, collection->target_addr); - vgic_its_invalidate_cache(kvm); - return update_affinity(ite->irq, vcpu); }
It is not necessary to invalidate the lpi translation cache when the virtual machine executes the movi instruction to adjust the affinity of the interrupt. Irqbalance will adjust the interrupt affinity in a short period of time to achieve the purpose of interrupting load balancing, but this does not affect the contents of the lpi translation cache. Signed-off-by: Xiangyou Xie <xiexiangyou@huawei.com> --- virt/kvm/arm/vgic/vgic-its.c | 2 -- 1 file changed, 2 deletions(-)