| Message ID | 20190923122454.9888-5-baolu.lu@linux.intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Use 1st-level for DMA remapping in guest | expand |
On Mon, Sep 23, 2019 at 08:24:54PM +0800, Lu Baolu wrote: > +/* > + * Check and return whether first level is used by default for > + * DMA translation. > + */ > +static bool first_level_by_default(void) > +{ > + struct dmar_drhd_unit *drhd; > + struct intel_iommu *iommu; > + > + rcu_read_lock(); > + for_each_active_iommu(iommu, drhd) > + if (!sm_supported(iommu) || > + !ecap_flts(iommu->ecap) || > + !cap_caching_mode(iommu->cap)) > + return false; > + rcu_read_unlock(); > + > + return true; > +} "If no caching mode, then we will not use 1st level." Hmm, does the vIOMMU needs to support caching-mode if with the solution you proposed here? Caching mode is only necessary for shadowing AFAICT, and after all you're going to use full-nested, then... then I would think it's not needed. And if so, with this patch 1st level will be disabled. Sounds like a paradox... I'm thinking what would be the big picture for this to work now: For the vIOMMU, instead of exposing the caching-mode, I'm thinking maybe we should expose it with ecap.FLTS=1 while we can keep ecap.SLTS=0 then it's natural that we can only use 1st level translation in the guest for all the domains (and I assume such an ecap value should never happen on real hardware, am I right?). Regards,
> From: Peter Xu [mailto:peterx@redhat.com] > Sent: Wednesday, September 25, 2019 2:50 PM > > On Mon, Sep 23, 2019 at 08:24:54PM +0800, Lu Baolu wrote: > > +/* > > + * Check and return whether first level is used by default for > > + * DMA translation. > > + */ > > +static bool first_level_by_default(void) > > +{ > > + struct dmar_drhd_unit *drhd; > > + struct intel_iommu *iommu; > > + > > + rcu_read_lock(); > > + for_each_active_iommu(iommu, drhd) > > + if (!sm_supported(iommu) || > > + !ecap_flts(iommu->ecap) || > > + !cap_caching_mode(iommu->cap)) > > + return false; > > + rcu_read_unlock(); > > + > > + return true; > > +} > > "If no caching mode, then we will not use 1st level." > > Hmm, does the vIOMMU needs to support caching-mode if with the > solution you proposed here? Caching mode is only necessary for > shadowing AFAICT, and after all you're going to use full-nested, > then... then I would think it's not needed. And if so, with this > patch 1st level will be disabled. Sounds like a paradox... > > I'm thinking what would be the big picture for this to work now: For > the vIOMMU, instead of exposing the caching-mode, I'm thinking maybe > we should expose it with ecap.FLTS=1 while we can keep ecap.SLTS=0 > then it's natural that we can only use 1st level translation in the > guest for all the domains (and I assume such an ecap value should > never happen on real hardware, am I right?). > yes, that's also the picture in my mind. :-) Thanks Kevin
diff --git a/drivers/iommu/intel-iommu.c b/drivers/iommu/intel-iommu.c index 103480016010..d539e6a6c3dd 100644 --- a/drivers/iommu/intel-iommu.c +++ b/drivers/iommu/intel-iommu.c @@ -1722,6 +1722,26 @@ static void free_dmar_iommu(struct intel_iommu *iommu) #endif } +/* + * Check and return whether first level is used by default for + * DMA translation. + */ +static bool first_level_by_default(void) +{ + struct dmar_drhd_unit *drhd; + struct intel_iommu *iommu; + + rcu_read_lock(); + for_each_active_iommu(iommu, drhd) + if (!sm_supported(iommu) || + !ecap_flts(iommu->ecap) || + !cap_caching_mode(iommu->cap)) + return false; + rcu_read_unlock(); + + return true; +} + static struct dmar_domain *alloc_domain(int flags) { struct dmar_domain *domain; @@ -1736,6 +1756,9 @@ static struct dmar_domain *alloc_domain(int flags) domain->has_iotlb_device = false; INIT_LIST_HEAD(&domain->devices); + if (first_level_by_default()) + domain->flags |= DOMAIN_FLAG_FIRST_LEVEL_TRANS; + return domain; } @@ -2625,6 +2648,11 @@ static struct dmar_domain *dmar_insert_one_dev_info(struct intel_iommu *iommu, if (hw_pass_through && domain_type_is_si(domain)) ret = intel_pasid_setup_pass_through(iommu, domain, dev, PASID_RID2PASID); + else if (domain_type_is_flt(domain)) + ret = intel_pasid_setup_first_level(iommu, dev, + domain->pgd, PASID_RID2PASID, + domain->iommu_did[iommu->seq_id], + PASID_FLAG_SUPERVISOR_MODE); else ret = intel_pasid_setup_second_level(iommu, domain, dev, PASID_RID2PASID); @@ -5349,8 +5377,14 @@ static int aux_domain_add_dev(struct dmar_domain *domain, goto attach_failed; /* Setup the PASID entry for mediated devices: */ - ret = intel_pasid_setup_second_level(iommu, domain, dev, - domain->default_pasid); + if (domain_type_is_flt(domain)) + ret = intel_pasid_setup_first_level(iommu, dev, + domain->pgd, domain->default_pasid, + domain->iommu_did[iommu->seq_id], + PASID_FLAG_SUPERVISOR_MODE); + else + ret = intel_pasid_setup_second_level(iommu, domain, dev, + domain->default_pasid); if (ret) goto table_failed; spin_unlock(&iommu->lock); @@ -5583,7 +5617,8 @@ static phys_addr_t intel_iommu_iova_to_phys(struct iommu_domain *domain, int level = 0; u64 phys = 0; - if (dmar_domain->flags & DOMAIN_FLAG_LOSE_CHILDREN) + if ((dmar_domain->flags & DOMAIN_FLAG_LOSE_CHILDREN) || + (dmar_domain->flags & DOMAIN_FLAG_FIRST_LEVEL_TRANS)) return 0; pte = pfn_to_dma_pte(dmar_domain, iova >> VTD_PAGE_SHIFT, &level);
This checks whether a domain should use first level page table for map/unmap. And if so, we should attach the domain to the device in first level translation mode. Cc: Ashok Raj <ashok.raj@intel.com> Cc: Jacob Pan <jacob.jun.pan@linux.intel.com> Cc: Kevin Tian <kevin.tian@intel.com> Cc: Liu Yi L <yi.l.liu@intel.com> Cc: Yi Sun <yi.y.sun@linux.intel.com> Cc: Sanjay Kumar <sanjay.k.kumar@intel.com> Signed-off-by: Lu Baolu <baolu.lu@linux.intel.com> --- drivers/iommu/intel-iommu.c | 41 ++++++++++++++++++++++++++++++++++--- 1 file changed, 38 insertions(+), 3 deletions(-)