From patchwork Wed Sep 25 11:19:41 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marc Zyngier X-Patchwork-Id: 11160461 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 3D8AF76 for ; Wed, 25 Sep 2019 11:20:13 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 1BB2D21D7E for ; Wed, 25 Sep 2019 11:20:05 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1569410409; bh=vfJ7RHSxrXG/7ljb+1JrzuuGrPoIvX2J5KtrGiADNTw=; h=From:To:Cc:Subject:Date:In-Reply-To:References:List-ID:From; b=beaPWz/pLjSa8p+EpNtTBp2VQ8vkBwT4A12uXobiaimXUAwgaG34/YpH8xLTczgv2 cXH9cu5UyhtIMATKPrmhaSqJbNneMR+wG3SNK82wjHQkQRnkKQzdoTQK626FTfs9gr gZmtISnHOEtRwgtUH32DnLffmEO62/oKtHr3gmUE= Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2390954AbfIYLUE (ORCPT ); Wed, 25 Sep 2019 07:20:04 -0400 Received: from foss.arm.com ([217.140.110.172]:46926 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2391063AbfIYLUD (ORCPT ); Wed, 25 Sep 2019 07:20:03 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id D25181597; Wed, 25 Sep 2019 04:20:02 -0700 (PDT) Received: from filthy-habits.cambridge.arm.com (filthy-habits.cambridge.arm.com [10.1.197.61]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 99AE73F694; Wed, 25 Sep 2019 04:20:01 -0700 (PDT) From: Marc Zyngier To: linux-arm-kernel@lists.infradead.org, kvmarm@lists.cs.columbia.edu, kvm@vger.kernel.org Cc: Will Deacon , Mark Rutland , Catalin Marinas , James Morse , Suzuki K Poulose , Julien Thierry Subject: [PATCH 5/5] arm64: Enable and document ARM errata 1319367 and 1319537 Date: Wed, 25 Sep 2019 12:19:41 +0100 Message-Id: <20190925111941.88103-6-maz@kernel.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190925111941.88103-1-maz@kernel.org> References: <20190925111941.88103-1-maz@kernel.org> MIME-Version: 1.0 Sender: kvm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Now that everything is in place, let's get the ball rolling by allowing the corresponding config option to be selected. Also add the required information to silicon_arrata.rst. Signed-off-by: Marc Zyngier Acked-by: Catalin Marinas --- Documentation/arm64/silicon-errata.rst | 4 ++++ arch/arm64/Kconfig | 10 ++++++++++ 2 files changed, 14 insertions(+) diff --git a/Documentation/arm64/silicon-errata.rst b/Documentation/arm64/silicon-errata.rst index 3e57d09246e6..b90a977fc748 100644 --- a/Documentation/arm64/silicon-errata.rst +++ b/Documentation/arm64/silicon-errata.rst @@ -70,8 +70,12 @@ stable kernels. +----------------+-----------------+-----------------+-----------------------------+ | ARM | Cortex-A57 | #834220 | ARM64_ERRATUM_834220 | +----------------+-----------------+-----------------+-----------------------------+ +| ARM | Cortex-A57 | #1319537 | ARM64_ERRATUM_1319367 | ++----------------+-----------------+-----------------+-----------------------------+ | ARM | Cortex-A72 | #853709 | N/A | +----------------+-----------------+-----------------+-----------------------------+ +| ARM | Cortex-A72 | #1319367 | ARM64_ERRATUM_1319367 | ++----------------+-----------------+-----------------+-----------------------------+ | ARM | Cortex-A73 | #858921 | ARM64_ERRATUM_858921 | +----------------+-----------------+-----------------+-----------------------------+ | ARM | Cortex-A55 | #1024718 | ARM64_ERRATUM_1024718 | diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig index 3adcec05b1f6..c50cd4f83bc4 100644 --- a/arch/arm64/Kconfig +++ b/arch/arm64/Kconfig @@ -523,6 +523,16 @@ config ARM64_ERRATUM_1286807 invalidated has been observed by other observers. The workaround repeats the TLBI+DSB operation. +config ARM64_ERRATUM_1319367 + bool "Cortex-A57/A72: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation" + default y + help + This option adds work arounds for ARM Cortex-A57 erratum 1319537 + and A72 erratum 1319367 + + Cortex-A57 and A72 cores could end-up with corrupted TLBs by + speculating an AT instruction during a guest context switch. + If unsure, say Y. config ARM64_ERRATUM_1463225