| Message ID | 20190925213721.21245-3-bigeasy@linutronix.de (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | [1/2] KVM: x86: svm: Pass XSAVES to guest if available on host | expand |
On Wed, Sep 25, 2019 at 2:37 PM Sebastian Andrzej Siewior <bigeasy@linutronix.de> wrote: > > I was surprised to see that the guest reported `fxsave_leak' while the > host did not. After digging deeper I noticed that the bits are simply > masked out during enumeration. > The XSAVEERPTR feature is actually a bug fix on AMD which means the > kernel can disable a workaround. > While here, I've seen that CLZERO is also masked out. This opcode is > unprivilged so exposing it to the guest should not make any difference. > > Pass CLZERO and XSAVEERPTR to the guest if available on the host. > > Signed-off-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de> > --- > arch/x86/kvm/cpuid.c | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/arch/x86/kvm/cpuid.c b/arch/x86/kvm/cpuid.c > index 22c2720cd948e..0ae9194d0f4d2 100644 > --- a/arch/x86/kvm/cpuid.c > +++ b/arch/x86/kvm/cpuid.c > @@ -473,6 +473,7 @@ static inline int __do_cpuid_func(struct kvm_cpuid_entry2 *entry, u32 function, > > /* cpuid 0x80000008.ebx */ > const u32 kvm_cpuid_8000_0008_ebx_x86_features = > + F(CLZERO) | F(XSAVEERPTR) | > F(WBNOINVD) | F(AMD_IBPB) | F(AMD_IBRS) | F(AMD_SSBD) | F(VIRT_SSBD) | > F(AMD_SSB_NO) | F(AMD_STIBP) | F(AMD_STIBP_ALWAYS_ON); > > -- > 2.23.0 Didn't someone just post "[PATCH] kvm: x86: Enumerate support for CLZERO instruction" yesterday? :-)
On 25/09/19 23:37, Sebastian Andrzej Siewior wrote: > I was surprised to see that the guest reported `fxsave_leak' while the > host did not. After digging deeper I noticed that the bits are simply > masked out during enumeration. > The XSAVEERPTR feature is actually a bug fix on AMD which means the > kernel can disable a workaround. > While here, I've seen that CLZERO is also masked out. This opcode is > unprivilged so exposing it to the guest should not make any difference. > > Pass CLZERO and XSAVEERPTR to the guest if available on the host. > > Signed-off-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de> > --- > arch/x86/kvm/cpuid.c | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/arch/x86/kvm/cpuid.c b/arch/x86/kvm/cpuid.c > index 22c2720cd948e..0ae9194d0f4d2 100644 > --- a/arch/x86/kvm/cpuid.c > +++ b/arch/x86/kvm/cpuid.c > @@ -473,6 +473,7 @@ static inline int __do_cpuid_func(struct kvm_cpuid_entry2 *entry, u32 function, > > /* cpuid 0x80000008.ebx */ > const u32 kvm_cpuid_8000_0008_ebx_x86_features = > + F(CLZERO) | F(XSAVEERPTR) | > F(WBNOINVD) | F(AMD_IBPB) | F(AMD_IBRS) | F(AMD_SSBD) | F(VIRT_SSBD) | > F(AMD_SSB_NO) | F(AMD_STIBP) | F(AMD_STIBP_ALWAYS_ON); > > Applied (on top of Jim's CLZERO patch, so removing the CLZERO reference in the commit message). Paolo
diff --git a/arch/x86/kvm/cpuid.c b/arch/x86/kvm/cpuid.c index 22c2720cd948e..0ae9194d0f4d2 100644 --- a/arch/x86/kvm/cpuid.c +++ b/arch/x86/kvm/cpuid.c @@ -473,6 +473,7 @@ static inline int __do_cpuid_func(struct kvm_cpuid_entry2 *entry, u32 function, /* cpuid 0x80000008.ebx */ const u32 kvm_cpuid_8000_0008_ebx_x86_features = + F(CLZERO) | F(XSAVEERPTR) | F(WBNOINVD) | F(AMD_IBPB) | F(AMD_IBRS) | F(AMD_SSBD) | F(VIRT_SSBD) | F(AMD_SSB_NO) | F(AMD_STIBP) | F(AMD_STIBP_ALWAYS_ON);
I was surprised to see that the guest reported `fxsave_leak' while the host did not. After digging deeper I noticed that the bits are simply masked out during enumeration. The XSAVEERPTR feature is actually a bug fix on AMD which means the kernel can disable a workaround. While here, I've seen that CLZERO is also masked out. This opcode is unprivilged so exposing it to the guest should not make any difference. Pass CLZERO and XSAVEERPTR to the guest if available on the host. Signed-off-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de> --- arch/x86/kvm/cpuid.c | 1 + 1 file changed, 1 insertion(+)