| Message ID | 20190930142508.25102-2-alexandru.elisei@arm.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | arm64: Add code generation test | expand |
On Mon, Sep 30, 2019 at 03:25:06PM +0100, Alexandru Elisei wrote: > Linux commit d0b7a302d58a made it abundantly clear that certain CPU > implementations require an ISB after a DSB. Add the missing ISB to > flush_tlb_page. No changes are required for flush_tlb_all, as the function > already had the ISB. > > Signed-off-by: Alexandru Elisei <alexandru.elisei@arm.com> > --- > lib/arm64/asm/mmu.h | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/lib/arm64/asm/mmu.h b/lib/arm64/asm/mmu.h > index fa554b0c20ae..72d75eafc882 100644 > --- a/lib/arm64/asm/mmu.h > +++ b/lib/arm64/asm/mmu.h > @@ -24,6 +24,7 @@ static inline void flush_tlb_page(unsigned long vaddr) > dsb(ishst); > asm("tlbi vaae1is, %0" :: "r" (page)); > dsb(ish); > + isb(); > } > > static inline void flush_dcache_addr(unsigned long vaddr) > -- > 2.20.1 > Reviewed-by: Andrew Jones <drjones@redhat.com>
diff --git a/lib/arm64/asm/mmu.h b/lib/arm64/asm/mmu.h index fa554b0c20ae..72d75eafc882 100644 --- a/lib/arm64/asm/mmu.h +++ b/lib/arm64/asm/mmu.h @@ -24,6 +24,7 @@ static inline void flush_tlb_page(unsigned long vaddr) dsb(ishst); asm("tlbi vaae1is, %0" :: "r" (page)); dsb(ish); + isb(); } static inline void flush_dcache_addr(unsigned long vaddr)
Linux commit d0b7a302d58a made it abundantly clear that certain CPU implementations require an ISB after a DSB. Add the missing ISB to flush_tlb_page. No changes are required for flush_tlb_all, as the function already had the ISB. Signed-off-by: Alexandru Elisei <alexandru.elisei@arm.com> --- lib/arm64/asm/mmu.h | 1 + 1 file changed, 1 insertion(+)