diff mbox series

KVM: nVMX: WARN on failure to set IA32_PERF_GLOBAL_CTRL

Message ID 20191214003358.169496-1-oupton@google.com (mailing list archive)
State New, archived
Headers show
Series KVM: nVMX: WARN on failure to set IA32_PERF_GLOBAL_CTRL | expand

Commit Message

Oliver Upton Dec. 14, 2019, 12:33 a.m. UTC
Writes to MSR_CORE_PERF_GLOBAL_CONTROL should never fail if the VM-exit
and VM-entry controls are exposed to L1. Promote the checks to perform a
full WARN if kvm_set_msr() fails and remove the now unused macro
SET_MSR_OR_WARN().

Suggested-by: Sean Christopherson <sean.j.christopherson@intel.com>
Cc: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Oliver Upton <oupton@google.com>
---
 arch/x86/kvm/vmx/nested.c | 18 ++++--------------
 1 file changed, 4 insertions(+), 14 deletions(-)

Comments

Sean Christopherson Dec. 17, 2019, 11:22 p.m. UTC | #1
On Fri, Dec 13, 2019 at 04:33:58PM -0800, Oliver Upton wrote:
> Writes to MSR_CORE_PERF_GLOBAL_CONTROL should never fail if the VM-exit
> and VM-entry controls are exposed to L1. Promote the checks to perform a
> full WARN if kvm_set_msr() fails and remove the now unused macro
> SET_MSR_OR_WARN().
> 
> Suggested-by: Sean Christopherson <sean.j.christopherson@intel.com>
> Cc: Paolo Bonzini <pbonzini@redhat.com>
> Signed-off-by: Oliver Upton <oupton@google.com>
> ---

Reviewed-by: Sean Christopherson <sean.j.christopherson@intel.com>
Oliver Upton Jan. 18, 2020, 12:20 a.m. UTC | #2
On Tue, Dec 17, 2019 at 03:22:29PM -0800, Sean Christopherson wrote:
> On Fri, Dec 13, 2019 at 04:33:58PM -0800, Oliver Upton wrote:
> > Writes to MSR_CORE_PERF_GLOBAL_CONTROL should never fail if the VM-exit
> > and VM-entry controls are exposed to L1. Promote the checks to perform a
> > full WARN if kvm_set_msr() fails and remove the now unused macro
> > SET_MSR_OR_WARN().
> > 
> > Suggested-by: Sean Christopherson <sean.j.christopherson@intel.com>
> > Cc: Paolo Bonzini <pbonzini@redhat.com>
> > Signed-off-by: Oliver Upton <oupton@google.com>
> > ---
> 
> Reviewed-by: Sean Christopherson <sean.j.christopherson@intel.com>

Ping :)
Paolo Bonzini Jan. 18, 2020, 9:35 p.m. UTC | #3
On 14/12/19 01:33, Oliver Upton wrote:
> Writes to MSR_CORE_PERF_GLOBAL_CONTROL should never fail if the VM-exit
> and VM-entry controls are exposed to L1. Promote the checks to perform a
> full WARN if kvm_set_msr() fails and remove the now unused macro
> SET_MSR_OR_WARN().
> 
> Suggested-by: Sean Christopherson <sean.j.christopherson@intel.com>
> Cc: Paolo Bonzini <pbonzini@redhat.com>
> Signed-off-by: Oliver Upton <oupton@google.com>
> ---
>  arch/x86/kvm/vmx/nested.c | 18 ++++--------------
>  1 file changed, 4 insertions(+), 14 deletions(-)
> 
> diff --git a/arch/x86/kvm/vmx/nested.c b/arch/x86/kvm/vmx/nested.c
> index 4aea7d304beb..fb502c62ee94 100644
> --- a/arch/x86/kvm/vmx/nested.c
> +++ b/arch/x86/kvm/vmx/nested.c
> @@ -28,16 +28,6 @@ module_param(nested_early_check, bool, S_IRUGO);
>  	failed;								\
>  })
>  
> -#define SET_MSR_OR_WARN(vcpu, idx, data)				\
> -({									\
> -	bool failed = kvm_set_msr(vcpu, idx, data);			\
> -	if (failed)							\
> -		pr_warn_ratelimited(					\
> -				"%s cannot write MSR (0x%x, 0x%llx)\n",	\
> -				__func__, idx, data);			\
> -	failed;								\
> -})
> -
>  /*
>   * Hyper-V requires all of these, so mark them as supported even though
>   * they are just treated the same as all-context.
> @@ -2550,8 +2540,8 @@ static int prepare_vmcs02(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12,
>  		vcpu->arch.walk_mmu->inject_page_fault = vmx_inject_page_fault_nested;
>  
>  	if ((vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL) &&
> -	    SET_MSR_OR_WARN(vcpu, MSR_CORE_PERF_GLOBAL_CTRL,
> -			    vmcs12->guest_ia32_perf_global_ctrl))
> +	    WARN_ON_ONCE(kvm_set_msr(vcpu, MSR_CORE_PERF_GLOBAL_CTRL,
> +				     vmcs12->guest_ia32_perf_global_ctrl)))
>  		return -EINVAL;
>  
>  	kvm_rsp_write(vcpu, vmcs12->guest_rsp);
> @@ -3999,8 +3989,8 @@ static void load_vmcs12_host_state(struct kvm_vcpu *vcpu,
>  		vcpu->arch.pat = vmcs12->host_ia32_pat;
>  	}
>  	if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
> -		SET_MSR_OR_WARN(vcpu, MSR_CORE_PERF_GLOBAL_CTRL,
> -				vmcs12->host_ia32_perf_global_ctrl);
> +		WARN_ON_ONCE(kvm_set_msr(vcpu, MSR_CORE_PERF_GLOBAL_CTRL,
> +					 vmcs12->host_ia32_perf_global_ctrl));
>  
>  	/* Set L1 segment info according to Intel SDM
>  	    27.5.2 Loading Host Segment and Descriptor-Table Registers */
> 

Queued, thanks.

Paolo
diff mbox series

Patch

diff --git a/arch/x86/kvm/vmx/nested.c b/arch/x86/kvm/vmx/nested.c
index 4aea7d304beb..fb502c62ee94 100644
--- a/arch/x86/kvm/vmx/nested.c
+++ b/arch/x86/kvm/vmx/nested.c
@@ -28,16 +28,6 @@  module_param(nested_early_check, bool, S_IRUGO);
 	failed;								\
 })
 
-#define SET_MSR_OR_WARN(vcpu, idx, data)				\
-({									\
-	bool failed = kvm_set_msr(vcpu, idx, data);			\
-	if (failed)							\
-		pr_warn_ratelimited(					\
-				"%s cannot write MSR (0x%x, 0x%llx)\n",	\
-				__func__, idx, data);			\
-	failed;								\
-})
-
 /*
  * Hyper-V requires all of these, so mark them as supported even though
  * they are just treated the same as all-context.
@@ -2550,8 +2540,8 @@  static int prepare_vmcs02(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12,
 		vcpu->arch.walk_mmu->inject_page_fault = vmx_inject_page_fault_nested;
 
 	if ((vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL) &&
-	    SET_MSR_OR_WARN(vcpu, MSR_CORE_PERF_GLOBAL_CTRL,
-			    vmcs12->guest_ia32_perf_global_ctrl))
+	    WARN_ON_ONCE(kvm_set_msr(vcpu, MSR_CORE_PERF_GLOBAL_CTRL,
+				     vmcs12->guest_ia32_perf_global_ctrl)))
 		return -EINVAL;
 
 	kvm_rsp_write(vcpu, vmcs12->guest_rsp);
@@ -3999,8 +3989,8 @@  static void load_vmcs12_host_state(struct kvm_vcpu *vcpu,
 		vcpu->arch.pat = vmcs12->host_ia32_pat;
 	}
 	if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
-		SET_MSR_OR_WARN(vcpu, MSR_CORE_PERF_GLOBAL_CTRL,
-				vmcs12->host_ia32_perf_global_ctrl);
+		WARN_ON_ONCE(kvm_set_msr(vcpu, MSR_CORE_PERF_GLOBAL_CTRL,
+					 vmcs12->host_ia32_perf_global_ctrl));
 
 	/* Set L1 segment info according to Intel SDM
 	    27.5.2 Loading Host Segment and Descriptor-Table Registers */