@@ -17,6 +17,9 @@
#define ARCH_TIMER_CTL_ISTATUS (1 << 2)
static void *gic_ispendr;
+static void *gic_isenabler;
+static void *gic_icenabler;
+
static bool ptimer_unsupported;
static void ptimer_unsupported_handler(struct pt_regs *regs, unsigned int esr)
@@ -132,19 +135,12 @@ static struct timer_info ptimer_info = {
static void set_timer_irq_enabled(struct timer_info *info, bool enabled)
{
- u32 val = 0;
+ u32 val = 1 << PPI(info->irq);
if (enabled)
- val = 1 << PPI(info->irq);
-
- switch (gic_version()) {
- case 2:
- writel(val, gicv2_dist_base() + GICD_ISENABLER + 0);
- break;
- case 3:
- writel(val, gicv3_sgi_base() + GICR_ISENABLER0);
- break;
- }
+ writel(val, gic_isenabler);
+ else
+ writel(val, gic_icenabler);
}
static void irq_handler(struct pt_regs *regs)
@@ -306,9 +302,13 @@ static void test_init(void)
switch (gic_version()) {
case 2:
gic_ispendr = gicv2_dist_base() + GICD_ISPENDR;
+ gic_isenabler = gicv2_dist_base() + GICD_ISENABLER;
+ gic_icenabler = gicv2_dist_base() + GICD_ICENABLER;
break;
case 3:
gic_ispendr = gicv3_sgi_base() + GICD_ISPENDR;
+ gic_isenabler = gicv3_sgi_base() + GICR_ISENABLER0;
+ gic_icenabler = gicv3_sgi_base() + GICR_ICENABLER0;
break;
}
@@ -31,6 +31,7 @@
/* Re-Distributor registers, offsets from SGI_base */
#define GICR_IGROUPR0 GICD_IGROUPR
#define GICR_ISENABLER0 GICD_ISENABLER
+#define GICR_ICENABLER0 GICD_ICENABLER
#define GICR_IPRIORITYR0 GICD_IPRIORITYR
#define ICC_SGI1R_AFFINITY_1_SHIFT 16
@@ -15,6 +15,7 @@
#define GICD_IIDR 0x0008
#define GICD_IGROUPR 0x0080
#define GICD_ISENABLER 0x0100
+#define GICD_ICENABLER 0x0180
#define GICD_ISPENDR 0x0200
#define GICD_ICPENDR 0x0280
#define GICD_ISACTIVER 0x0300