From patchwork Fri Mar 20 09:24:20 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Eric Auger X-Patchwork-Id: 11448721 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id DE3851392 for ; Fri, 20 Mar 2020 09:25:09 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id BA7BC20775 for ; Fri, 20 Mar 2020 09:25:09 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=redhat.com header.i=@redhat.com header.b="HR9lNlrN" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727141AbgCTJZI (ORCPT ); Fri, 20 Mar 2020 05:25:08 -0400 Received: from us-smtp-delivery-74.mimecast.com ([63.128.21.74]:57533 "EHLO us-smtp-delivery-74.mimecast.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727002AbgCTJZH (ORCPT ); Fri, 20 Mar 2020 05:25:07 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1584696307; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=Zl9FDtxwOI/FksilYChFV1G9aFjsIXI5j5prCQSwE+w=; b=HR9lNlrNuuAQg7GZFmKphGaTQspCDTG0TSVX51fFTWpqOHTLoMu19Sh2FQ6BlqDv2w/fpj VooXgWtHXWlraOnv2yGCNvq4yE0yyNVnbXlfG1K2r4SB7MemdR8AtwTfJN1QATxaKVsUoN Pk487DtKw8fixgPUCWtBQuAooauQs7M= Received: from mimecast-mx01.redhat.com (mimecast-mx01.redhat.com [209.132.183.4]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-104-kec4IxgiNq-1dn2OBz0ktw-1; Fri, 20 Mar 2020 05:25:05 -0400 X-MC-Unique: kec4IxgiNq-1dn2OBz0ktw-1 Received: from smtp.corp.redhat.com (int-mx06.intmail.prod.int.phx2.redhat.com [10.5.11.16]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id 10FCB8017CC; Fri, 20 Mar 2020 09:25:02 +0000 (UTC) Received: from laptop.redhat.com (ovpn-113-142.ams2.redhat.com [10.36.113.142]) by smtp.corp.redhat.com (Postfix) with ESMTP id E83075C1D8; Fri, 20 Mar 2020 09:24:58 +0000 (UTC) From: Eric Auger To: eric.auger.pro@gmail.com, eric.auger@redhat.com, maz@kernel.org, kvmarm@lists.cs.columbia.edu, kvm@vger.kernel.org, qemu-devel@nongnu.org, qemu-arm@nongnu.org Cc: drjones@redhat.com, andre.przywara@arm.com, peter.maydell@linaro.org, yuzenghui@huawei.com, alexandru.elisei@arm.com, thuth@redhat.com Subject: [kvm-unit-tests PATCH v7 05/13] arm/arm64: gicv3: Set the LPI config and pending tables Date: Fri, 20 Mar 2020 10:24:20 +0100 Message-Id: <20200320092428.20880-6-eric.auger@redhat.com> In-Reply-To: <20200320092428.20880-1-eric.auger@redhat.com> References: <20200320092428.20880-1-eric.auger@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.16 Sender: kvm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Allocate the LPI configuration and per re-distributor pending table. Set redistributor's PROPBASER and PENDBASER. The LPIs are enabled by default in the config table. Also introduce a helper routine that allows to set the pending table bit for a given LPI and macros to set/get its configuration. Signed-off-by: Eric Auger Reviewed-by: Zenghui Yu --- v5 -> v6: - fix the assert() - remove GICR_PROPBASER_IDBITS_MASK - remove gicv3_lpi_set_config and gicv3_lpi_get_config declarations and move macros in this patch v4 -> v5: - Moved some reformattings previously done in "arm/arm64: ITS: its_enable_defaults", in this patch - added assert(!gicv3_redist_base()) in gicv3_lpi_alloc_tables() - revert for_each_present_cpu() change v2 -> v3: - Move the helpers in lib/arm/gic-v3.c and prefix them with "gicv3_" and add _lpi prefix too v1 -> v2: - remove memory attributes --- lib/arm/asm/gic-v3.h | 17 ++++++++++++++ lib/arm/gic-v3.c | 53 ++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 70 insertions(+) diff --git a/lib/arm/asm/gic-v3.h b/lib/arm/asm/gic-v3.h index 47df051..fedffa8 100644 --- a/lib/arm/asm/gic-v3.h +++ b/lib/arm/asm/gic-v3.h @@ -50,6 +50,13 @@ #define MPIDR_TO_SGI_AFFINITY(cluster_id, level) \ (MPIDR_AFFINITY_LEVEL(cluster_id, level) << ICC_SGI1R_AFFINITY_## level ## _SHIFT) +#define GICR_PENDBASER_PTZ BIT_ULL(62) + +#define LPI_PROP_GROUP1 (1 << 1) +#define LPI_PROP_ENABLED (1 << 0) +#define LPI_PROP_DEFAULT_PRIO 0xa0 +#define LPI_PROP_DEFAULT (LPI_PROP_DEFAULT_PRIO | LPI_PROP_GROUP1 | LPI_PROP_ENABLED) + #include #ifndef __ASSEMBLY__ @@ -66,6 +73,8 @@ struct gicv3_data { void *dist_base; void *redist_bases[GICV3_NR_REDISTS]; void *redist_base[NR_CPUS]; + u8 *lpi_prop; + void *lpi_pend[NR_CPUS]; unsigned int irq_nr; }; extern struct gicv3_data gicv3_data; @@ -82,6 +91,8 @@ extern void gicv3_write_eoir(u32 irqstat); extern void gicv3_ipi_send_single(int irq, int cpu); extern void gicv3_ipi_send_mask(int irq, const cpumask_t *dest); extern void gicv3_set_redist_base(size_t stride); +extern void gicv3_lpi_set_clr_pending(int rdist, int n, bool set); +extern void gicv3_lpi_alloc_tables(void); static inline void gicv3_do_wait_for_rwp(void *base) { @@ -127,5 +138,11 @@ static inline u64 mpidr_uncompress(u32 compressed) return mpidr; } +#define gicv3_lpi_set_config(intid, value) ({ \ + gicv3_data.lpi_prop[LPI_OFFSET(intid)] = value; \ +}) + +#define gicv3_lpi_get_config(intid) (gicv3_data.lpi_prop[LPI_OFFSET(intid)]) + #endif /* !__ASSEMBLY__ */ #endif /* _ASMARM_GIC_V3_H_ */ diff --git a/lib/arm/gic-v3.c b/lib/arm/gic-v3.c index feecb5e..6cf1d1d 100644 --- a/lib/arm/gic-v3.c +++ b/lib/arm/gic-v3.c @@ -5,6 +5,7 @@ */ #include #include +#include void gicv3_set_redist_base(size_t stride) { @@ -147,3 +148,55 @@ void gicv3_ipi_send_single(int irq, int cpu) cpumask_set_cpu(cpu, &dest); gicv3_ipi_send_mask(irq, &dest); } + +#if defined(__aarch64__) + +/* + * alloc_lpi_tables - Allocate LPI config and pending tables + * and set PROPBASER (shared by all rdistributors) and per + * redistributor PENDBASER. + * + * gicv3_set_redist_base() must be called before + */ +void gicv3_lpi_alloc_tables(void) +{ + unsigned long n = SZ_64K >> PAGE_SHIFT; + unsigned long order = fls(n); + u64 prop_val; + int cpu; + + assert(gicv3_redist_base()); + + gicv3_data.lpi_prop = alloc_pages(order); + + /* ID bits = 13, ie. up to 14b LPI INTID */ + prop_val = (u64)(virt_to_phys(gicv3_data.lpi_prop)) | 13; + + for_each_present_cpu(cpu) { + u64 pend_val; + void *ptr; + + ptr = gicv3_data.redist_base[cpu]; + + writeq(prop_val, ptr + GICR_PROPBASER); + + gicv3_data.lpi_pend[cpu] = alloc_pages(order); + pend_val = (u64)(virt_to_phys(gicv3_data.lpi_pend[cpu])); + writeq(pend_val, ptr + GICR_PENDBASER); + } +} + +void gicv3_lpi_set_clr_pending(int rdist, int n, bool set) +{ + u8 *ptr = gicv3_data.lpi_pend[rdist]; + u8 mask = 1 << (n % 8), byte; + + ptr += (n / 8); + byte = *ptr; + if (set) + byte |= mask; + else + byte &= ~mask; + *ptr = byte; +} +#endif /* __aarch64__ */