From patchwork Thu Apr 2 14:52:21 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Eric Auger X-Patchwork-Id: 11470921 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 454331668 for ; Thu, 2 Apr 2020 14:53:35 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 23CA620784 for ; Thu, 2 Apr 2020 14:53:35 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=redhat.com header.i=@redhat.com header.b="TZaFdIJq" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2388902AbgDBOxe (ORCPT ); Thu, 2 Apr 2020 10:53:34 -0400 Received: from us-smtp-1.mimecast.com ([207.211.31.81]:40281 "EHLO us-smtp-delivery-1.mimecast.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S2388888AbgDBOxe (ORCPT ); Thu, 2 Apr 2020 10:53:34 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1585839212; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=Hf/vbu6ZInL6FP9HtFkeRkJlUrXIEdFFlVwfWy4rNEM=; b=TZaFdIJqsFTcTPzDtB8LVTR/tABKvy1NynNIOLEPbusisRKuKlc1fsiCVTStM/YmgYJ15b /47cmzzGc5BRuN7DnWvojN/DDJ8p6jDHP4RnIbdbAUv/UAPXUUbICMVKnz6wG5aShOddG5 J4kRPjwfWZMeJgZMOOajdppPbSfZPAI= Received: from mimecast-mx01.redhat.com (mimecast-mx01.redhat.com [209.132.183.4]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-407-tBZF-ZG_M0S_ippWcwicJA-1; Thu, 02 Apr 2020 10:53:29 -0400 X-MC-Unique: tBZF-ZG_M0S_ippWcwicJA-1 Received: from smtp.corp.redhat.com (int-mx04.intmail.prod.int.phx2.redhat.com [10.5.11.14]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id 68182107ACC9; Thu, 2 Apr 2020 14:53:27 +0000 (UTC) Received: from laptop.redhat.com (ovpn-112-58.ams2.redhat.com [10.36.112.58]) by smtp.corp.redhat.com (Postfix) with ESMTP id 45DF25D9C9; Thu, 2 Apr 2020 14:53:22 +0000 (UTC) From: Eric Auger To: eric.auger.pro@gmail.com, eric.auger@redhat.com, maz@kernel.org, kvmarm@lists.cs.columbia.edu, kvm@vger.kernel.org, qemu-devel@nongnu.org, qemu-arm@nongnu.org Cc: drjones@redhat.com, andre.przywara@arm.com, peter.maydell@linaro.org, yuzenghui@huawei.com, alexandru.elisei@arm.com, thuth@redhat.com Subject: [kvm-unit-tests PATCH v8 07/13] arm/arm64: ITS: its_enable_defaults Date: Thu, 2 Apr 2020 16:52:21 +0200 Message-Id: <20200402145227.20109-8-eric.auger@redhat.com> In-Reply-To: <20200402145227.20109-1-eric.auger@redhat.com> References: <20200402145227.20109-1-eric.auger@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.14 Sender: kvm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org its_enable_defaults() enable LPIs at redistributor level and ITS level. gicv3_enable_defaults must be called before. Signed-off-by: Eric Auger Reviewed-by: Zenghui Yu --- v6 -> v7: - use for_each_present_cpu in its_enable_defaults v5 -> v6: - gicv3_lpi_set/get_config introduced before this patch - dist/redist in commit msg - Added Zenghui's R-b v4 -> v5: - some reformattings moved to earlier patch - add assert(!gicv3_redist_base()) in alloc_lpi_tables() - revert the usage of for_each_present_cpu() v3 -> v4: - use GITS_BASER_INDIRECT & GITS_BASER_VALID in its_setup_baser() - don't parse BASERs again in its_enable_defaults - rename its_setup_baser into its_baser_alloc_table - All allocations moved to the init function - squashed "arm/arm64: gicv3: Enable/Disable LPIs at re-distributor level" into this patch - introduce gicv3_lpi_rdist_enable and gicv3_lpi_rdist_disable - pend and prop table bases stored as virt addresses - move some init functions from enable() to its_init - removed GICR_PROPBASER_IDBITS_MASK - introduced LPI_OFFSET - lpi_prop becomes u8 * - gicv3_lpi_set_config/get_config became macro - renamed gicv3_lpi_set_pending_table_bit into gicv3_lpi_set_clr_pending v2 -> v3: - introduce its_setup_baser in this patch - squash "arm/arm64: ITS: Init the command queue" in this patch. --- lib/arm/asm/gic-v3.h | 6 ++++++ lib/arm/gic-v3.c | 25 +++++++++++++++++++++++++ lib/arm64/asm/gic-v3-its.h | 1 + lib/arm64/gic-v3-its.c | 13 +++++++++++++ 4 files changed, 45 insertions(+) diff --git a/lib/arm/asm/gic-v3.h b/lib/arm/asm/gic-v3.h index fedffa8..cb72922 100644 --- a/lib/arm/asm/gic-v3.h +++ b/lib/arm/asm/gic-v3.h @@ -57,6 +57,10 @@ #define LPI_PROP_DEFAULT_PRIO 0xa0 #define LPI_PROP_DEFAULT (LPI_PROP_DEFAULT_PRIO | LPI_PROP_GROUP1 | LPI_PROP_ENABLED) +#define LPI_ID_BASE 8192 +#define LPI(lpi) ((lpi) + LPI_ID_BASE) +#define LPI_OFFSET(intid) ((intid) - LPI_ID_BASE) + #include #ifndef __ASSEMBLY__ @@ -93,6 +97,8 @@ extern void gicv3_ipi_send_mask(int irq, const cpumask_t *dest); extern void gicv3_set_redist_base(size_t stride); extern void gicv3_lpi_set_clr_pending(int rdist, int n, bool set); extern void gicv3_lpi_alloc_tables(void); +extern void gicv3_lpi_rdist_enable(int redist); +extern void gicv3_lpi_rdist_disable(int redist); static inline void gicv3_do_wait_for_rwp(void *base) { diff --git a/lib/arm/gic-v3.c b/lib/arm/gic-v3.c index 6cf1d1d..a7e2cb8 100644 --- a/lib/arm/gic-v3.c +++ b/lib/arm/gic-v3.c @@ -199,4 +199,29 @@ void gicv3_lpi_set_clr_pending(int rdist, int n, bool set) byte &= ~mask; *ptr = byte; } + +static void gicv3_lpi_rdist_ctrl(u32 redist, bool set) +{ + void *ptr; + u64 val; + + assert(redist < nr_cpus); + + ptr = gicv3_data.redist_base[redist]; + val = readl(ptr + GICR_CTLR); + if (set) + val |= GICR_CTLR_ENABLE_LPIS; + else + val &= ~GICR_CTLR_ENABLE_LPIS; + writel(val, ptr + GICR_CTLR); +} + +void gicv3_lpi_rdist_enable(int redist) +{ + gicv3_lpi_rdist_ctrl(redist, true); +} +void gicv3_lpi_rdist_disable(int redist) +{ + gicv3_lpi_rdist_ctrl(redist, false); +} #endif /* __aarch64__ */ diff --git a/lib/arm64/asm/gic-v3-its.h b/lib/arm64/asm/gic-v3-its.h index c0bd58c..7e03e4c 100644 --- a/lib/arm64/asm/gic-v3-its.h +++ b/lib/arm64/asm/gic-v3-its.h @@ -92,5 +92,6 @@ extern struct its_data its_data; extern void its_parse_typer(void); extern void its_init(void); extern int its_baser_lookup(int i, struct its_baser *baser); +extern void its_enable_defaults(void); #endif /* _ASMARM64_GIC_V3_ITS_H_ */ diff --git a/lib/arm64/gic-v3-its.c b/lib/arm64/gic-v3-its.c index 04dde97..cf176b7 100644 --- a/lib/arm64/gic-v3-its.c +++ b/lib/arm64/gic-v3-its.c @@ -96,3 +96,16 @@ void its_init(void) its_cmd_queue_init(); } +/* must be called after gicv3_enable_defaults */ +void its_enable_defaults(void) +{ + int cpu; + + /* Allocate LPI config and pending tables */ + gicv3_lpi_alloc_tables(); + + for_each_present_cpu(cpu) + gicv3_lpi_rdist_enable(cpu); + + writel(GITS_CTLR_ENABLE, its_data.base + GITS_CTLR); +}