From patchwork Thu Aug 27 09:21:37 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yifei Jiang X-Patchwork-Id: 11740327 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 22B3013B6 for ; Thu, 27 Aug 2020 09:23:30 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 095D92177B for ; Thu, 27 Aug 2020 09:23:30 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728406AbgH0JX3 (ORCPT ); Thu, 27 Aug 2020 05:23:29 -0400 Received: from szxga04-in.huawei.com ([45.249.212.190]:10325 "EHLO huawei.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1728404AbgH0JWq (ORCPT ); Thu, 27 Aug 2020 05:22:46 -0400 Received: from DGGEMS402-HUB.china.huawei.com (unknown [172.30.72.59]) by Forcepoint Email with ESMTP id B030E6AA5F5D63F4845C; Thu, 27 Aug 2020 17:22:42 +0800 (CST) Received: from huawei.com (10.174.187.31) by DGGEMS402-HUB.china.huawei.com (10.3.19.202) with Microsoft SMTP Server id 14.3.487.0; Thu, 27 Aug 2020 17:22:36 +0800 From: Yifei Jiang To: , CC: , , , , , , , , , , , , , Yifei Jiang Subject: [PATCH RFC v3 14/14] target/riscv: Support virtual time context synchronization Date: Thu, 27 Aug 2020 17:21:37 +0800 Message-ID: <20200827092137.479-15-jiangyifei@huawei.com> X-Mailer: git-send-email 2.26.2.windows.1 In-Reply-To: <20200827092137.479-1-jiangyifei@huawei.com> References: <20200827092137.479-1-jiangyifei@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.174.187.31] X-CFilter-Loop: Reflected Sender: kvm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Add virtual time context description to vmstate_riscv_cpu. After cpu being loaded, virtual time context is updated to KVM. Signed-off-by: Yifei Jiang Signed-off-by: Yipeng Yin --- target/riscv/cpu.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index b698f4adbb..c6b207d201 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -496,11 +496,19 @@ static void riscv_cpu_init(Object *obj) cpu_set_cpustate_pointers(cpu); } +static int cpu_post_load(void *opaque, int version_id) +{ + RISCVCPU *cpu = opaque; + cpu->env.kvm_timer_dirty = true; + return 0; +} + #ifndef CONFIG_USER_ONLY static const VMStateDescription vmstate_riscv_cpu = { .name = "cpu", .version_id = 1, .minimum_version_id = 1, + .post_load = cpu_post_load, .fields = (VMStateField[]) { VMSTATE_UINTTL_ARRAY(env.gpr, RISCVCPU, 32), VMSTATE_UINT64_ARRAY(env.fpr, RISCVCPU, 32), @@ -514,6 +522,9 @@ static const VMStateDescription vmstate_riscv_cpu = { VMSTATE_UINTTL(env.sbadaddr, RISCVCPU), VMSTATE_UINTTL(env.mip, RISCVCPU), VMSTATE_UINTTL(env.satp, RISCVCPU), + VMSTATE_UINT64(env.kvm_timer_time, RISCVCPU), + VMSTATE_UINT64(env.kvm_timer_compare, RISCVCPU), + VMSTATE_UINT64(env.kvm_timer_state, RISCVCPU), VMSTATE_END_OF_LIST() } };