From patchwork Mon Aug 31 12:30:14 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anup Patel X-Patchwork-Id: 11746307 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 079B4618 for ; Mon, 31 Aug 2020 12:34:50 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id D46C620782 for ; Mon, 31 Aug 2020 12:34:49 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (2048-bit key) header.d=wdc.com header.i=@wdc.com header.b="OsXQGIkI"; dkim=pass (1024-bit key) header.d=sharedspace.onmicrosoft.com header.i=@sharedspace.onmicrosoft.com header.b="lgnsfbdM" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728320AbgHaMen (ORCPT ); Mon, 31 Aug 2020 08:34:43 -0400 Received: from esa1.hgst.iphmx.com ([68.232.141.245]:45740 "EHLO esa1.hgst.iphmx.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728158AbgHaMdM (ORCPT ); Mon, 31 Aug 2020 08:33:12 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=wdc.com; i=@wdc.com; q=dns/txt; s=dkim.wdc.com; t=1598877191; x=1630413191; h=from:to:cc:subject:date:message-id:in-reply-to: references:content-transfer-encoding:mime-version; bh=pIgjHGT351nvqKIA1ZstQ4mDprYRXkOk8LFgTcWAxMw=; b=OsXQGIkIgbF1E6nYmzfFcjUVf6tEa6b/y44Mtan/rSN+oeMGBxES2QAs lPiKaATTszXMytc5oOsCI63gug46QPJ3t5jdl5zn/5Ar7XjxekB5odWVr d9ThF08PtDeR7pU7gf+yf/Chuuq/JbbkKLdFPQk3Wlxjcj+o7FI9CvBtt tsKsSemTGJnz1kmjLVt6LSrk8tr6eDuLl6rPfYmvUgFm2pOeXL3uRdyw/ TANH1LA/q/TuPQ4wXnmX5QQIH9h3nL6Bknf34PyOC07OPS1PZgpnMg3pE Xp0yV+XYru69KLcLCfkjD4wCAHFiXNrSWV171fUqc3hFV9SV1yAri/W/9 g==; IronPort-SDR: yiIfi2DKIk6XtmTQSol7UTm+J2atu8iG5PYDvDN5eH9LRIVSiS2+2Iou1qDnOeBJAJZd/6g0Di CVZRxKzBAzsyQ0EvWWsn7ERTg9csquv7a6u8rYEogUI92/3F7Ge6mikpFwDZbnoxiOSU89Tq9e /QScFLmvFd/4lfwoSZbQGrlFRBa0eqPBoNtTKEG7baOvobmqI0ke7Hldvxd4aOOJCR6Cq9pdRd dWhdyAefQpBic26KY0mNWFeVctX0VRM6qnVQzqYeNqUnXtlj0DHP3qggt10FWvJT83onS2fQef xZM= X-IronPort-AV: E=Sophos;i="5.76,375,1592841600"; d="scan'208";a="255743425" Received: from mail-sn1nam02lp2054.outbound.protection.outlook.com (HELO NAM02-SN1-obe.outbound.protection.outlook.com) ([104.47.36.54]) by ob1.hgst.iphmx.com with ESMTP; 31 Aug 2020 20:32:00 +0800 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=YfEbdPwL3fSNJwsfyD+owOBvx31n+sPronFnx5UxnjOEQgV6sM7LbM6KjJ+VBUaNO/WtFBRJ+4gpaYMaZjjjpaiITavZ6Yb9ffa+NYYJibpa1dGPiwy64p73FGwM9RAmBnvkM+YjSZeJdtdAPYSF4/m20+m+6+4banumLWxgvrVeM1ZbaM55S/qBv8C1nn/VpF8on6tgVIksiVv7tKdrZG8cQVypqNKEl7t0AGdlP8wl/ZmK5bHvfe53KesYlV+5v6GDC60DA4Bpdv+l04o8WzTuosDJ0IczBT3Y6dBfNXxkjq2ms9FBCG5FRRPTisXl1ZKqlWq6N21YpHQXnll8Mg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=7pL/cFTO1qwFtdIzSGSJUC80DF5VIPtdikZ21+a3xX0=; b=oIQUQDo24SPlsgV8SrnNHyCdD4oZy8XCLJjb/6taVBUW+fE+y7bjE1HKzcdK+TPU+Ol5uoXa6l1e6D9aKBk8WMGEt+cVoQaKmleLjTao8uGO/fduIcSVtKwEZh+L3Ht5CgxzX0QYSGqKmasLQGoYzFQYFDbo2CG3iQyuAFeu9XzMoWcsyZ/jVAgltlhEd9jq6fSIGQHoElKnNJOwTACEO3/4iI4RA5OPD4YTFYuxKwBiqLUdJLFN1bgTWZF9tggCFd56k3BYBbEe75N26RB4TGhnPsmuxplGRbdyIfXOUEBclJm3dYU9i+GFwtFwlwlK7qJZpZpSyDmoI6HUE9YHcg== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=wdc.com; dmarc=pass action=none header.from=wdc.com; dkim=pass header.d=wdc.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sharedspace.onmicrosoft.com; s=selector2-sharedspace-onmicrosoft-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=7pL/cFTO1qwFtdIzSGSJUC80DF5VIPtdikZ21+a3xX0=; b=lgnsfbdMNDjmrANYcJZYcjGubgU0i99v3dAZFLflMGIcPjwtWQX2AIdBxMUAGedA0RXjyUqqPLVY/+EPOK1w44IESlxtmuaAruXCuLgtQEJK35krU/6dbAAsL7DEuj1I0GmpWq8pRVmt4dbr7x+llCNxilzt3N5Z8aqiNEOrc6c= Authentication-Results: dabbelt.com; dkim=none (message not signed) header.d=none;dabbelt.com; dmarc=none action=none header.from=wdc.com; Received: from DM6PR04MB6201.namprd04.prod.outlook.com (2603:10b6:5:127::32) by DM6PR04MB6092.namprd04.prod.outlook.com (2603:10b6:5:12b::19) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3326.23; Mon, 31 Aug 2020 12:32:00 +0000 Received: from DM6PR04MB6201.namprd04.prod.outlook.com ([fe80::607a:44ed:1477:83e]) by DM6PR04MB6201.namprd04.prod.outlook.com ([fe80::607a:44ed:1477:83e%7]) with mapi id 15.20.3326.025; Mon, 31 Aug 2020 12:32:00 +0000 From: Anup Patel To: Palmer Dabbelt , Palmer Dabbelt , Paul Walmsley , Albert Ou , Paolo Bonzini Cc: Alexander Graf , Atish Patra , Alistair Francis , Damien Le Moal , Anup Patel , kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Anup Patel , Jonathan Corbet , linux-doc@vger.kernel.org Subject: [PATCH v14 16/17] RISC-V: KVM: Document RISC-V specific parts of KVM API Date: Mon, 31 Aug 2020 18:00:14 +0530 Message-Id: <20200831123015.336047-17-anup.patel@wdc.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200831123015.336047-1-anup.patel@wdc.com> References: <20200831123015.336047-1-anup.patel@wdc.com> X-ClientProxiedBy: BM1PR0101CA0046.INDPRD01.PROD.OUTLOOK.COM (2603:1096:b00:1a::32) To DM6PR04MB6201.namprd04.prod.outlook.com (2603:10b6:5:127::32) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from 255.255.255.255 (255.255.255.255) by BM1PR0101CA0046.INDPRD01.PROD.OUTLOOK.COM (2603:1096:b00:1a::32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3326.19 via Frontend Transport; Mon, 31 Aug 2020 12:31:54 +0000 X-Mailer: git-send-email 2.25.1 X-Originating-IP: [103.15.57.192] X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-HT: Tenant X-MS-Office365-Filtering-Correlation-Id: 4050fc84-3eef-493d-212f-08d84da9db0e X-MS-TrafficTypeDiagnostic: DM6PR04MB6092: X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: WDCIPOUTBOUND: EOP-TRUE X-MS-Oob-TLC-OOBClassifiers: OLM:6430; X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: vx6AxrzMNvne23TLR/fk+Rrk+eBPwtIAff16iqEaejUbsHLjY1p//kYKP4Yb6D7FQcY4IdkxA7Y1jxqEeyG82NztpS0rFPYeng77OUeRwsenBxmreg3nK8tSoi0NoDtWnlq6sO3tkbC+T7kvPzyHoPLNN87BF3EiuHaoM+z5955kIe7Zg1UtIv5gYvWLNyzxT4WABeCd/efeLDXB1NxLVtFvNPZCN5nf+GjOvbr4V2LbK80QJE9LfzW+0y2UL+lrApfZmOIR6NQ4WwYF4IwZRYgYqh3/T52X6Ac/YHNeyLhjaqkVqW94Xaoff4K4mGNKtCKVS8SkkOyI5IgXXXNS7O9FX45w1W3Xg1BSnvzF0kHRnwmvSyYAz+e33F6O3GEacGTcEUXU/xwQwEReW+5RoA== X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:DM6PR04MB6201.namprd04.prod.outlook.com;PTR:;CAT:NONE;SFS:(4636009)(136003)(396003)(366004)(39860400002)(346002)(376002)(44832011)(966005)(6666004)(52116002)(8676002)(86362001)(36756003)(478600001)(6486002)(7416002)(30864003)(110136005)(8936002)(54906003)(83380400001)(66946007)(1076003)(66556008)(2906002)(26005)(186003)(66476007)(956004)(316002)(16576012)(4326008)(5660300002)(2616005);DIR:OUT;SFP:1102; X-MS-Exchange-AntiSpam-MessageData: V8kHUK/4o3qbuAhbtLngd66z/M6xPnNJgmTcE6psH4KZrGz9i1/AGU5LyGmNb6IoPoQ4obZZBRKJp5r5TO+JbmLzUFmEQR2lu983Oj4/X5++01aFYd/4H3/CBX60mcQJykn9iP/gRXUlweD7cdnGpEKZqU7G9hJbcPbNjncWQrEDtRhIdgyCY0+3s1Qy4jVyy8rTPQZHswbcLqxGE52TElI2qz1c6aCzRJ2IR2AYRtlrEKZ21OvrVA/dmIrS+dYQ9Zmn41nqOuX1OzGzDNFOU+GtW3+UsQ7dhu+XszX+ni1lkuaYxqt1qAxnhMquMWEqoTqZuVGcceFSA2KR1X+EQ804gl2HU7QqRSjXLxI61sL0j7XLM5qkbTfvf918BIB1IJ04uJXrSxJuLL0xovLz6jK0qWXqSjaXvNy6+Hw8Nm1IVZASFuLR+CM/A4pazqRrbTaroqUs4gJIpitBxehgcqTFBm8j8knjeoWjJue5gGTCSofhp8e/XCPea3n1qdnCzkSiD/bGd7fLqlfRpV6bdgvLPIe7fCRgi7F2uKkwufg7dXDHkwmnRVwWHI+t1iCFK0NuXKuAtycjh93cm3b1zeowyWxH82dxx9xWmNfO6jRAmwECR10dnd5s5EOo5GL1x+BAtcuD7bNlzJsI2ff/IQ== X-OriginatorOrg: wdc.com X-MS-Exchange-CrossTenant-Network-Message-Id: 4050fc84-3eef-493d-212f-08d84da9db0e X-MS-Exchange-CrossTenant-AuthSource: DM6PR04MB6201.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 31 Aug 2020 12:31:59.8859 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: b61c8803-16f3-4c35-9b17-6f65f441df86 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: 9mcSTB8kkwP5lWGPJPCtbU268zlTjxDyJrhYg1lnoBl8M7ajXxEQtwg4DNHECg9gnAePuakG7tJdJTyHk9XhcA== X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR04MB6092 Sender: kvm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Document RISC-V specific parts of the KVM API, such as: - The interrupt numbers passed to the KVM_INTERRUPT ioctl. - The states supported by the KVM_{GET,SET}_MP_STATE ioctls. - The registers supported by the KVM_{GET,SET}_ONE_REG interface and the encoding of those register ids. - The exit reason KVM_EXIT_RISCV_SBI for SBI calls forwarded to userspace tool. CC: Jonathan Corbet CC: linux-doc@vger.kernel.org Signed-off-by: Anup Patel --- Documentation/virt/kvm/api.rst | 193 +++++++++++++++++++++++++++++++-- 1 file changed, 184 insertions(+), 9 deletions(-) diff --git a/Documentation/virt/kvm/api.rst b/Documentation/virt/kvm/api.rst index eb3a1316f03e..b2f48e1adb11 100644 --- a/Documentation/virt/kvm/api.rst +++ b/Documentation/virt/kvm/api.rst @@ -513,7 +513,7 @@ translation mode. ------------------ :Capability: basic -:Architectures: x86, ppc, mips +:Architectures: x86, ppc, mips, riscv :Type: vcpu ioctl :Parameters: struct kvm_interrupt (in) :Returns: 0 on success, negative on failure. @@ -582,6 +582,23 @@ interrupt number dequeues the interrupt. This is an asynchronous vcpu ioctl and can be invoked from any thread. +RISC-V: +^^^^^^^ + +Queues an external interrupt to be injected into the virutal CPU. This ioctl +is overloaded with 2 different irq values: + +a) KVM_INTERRUPT_SET + + This sets external interrupt for a virtual CPU and it will receive + once it is ready. + +b) KVM_INTERRUPT_UNSET + + This clears pending external interrupt for a virtual CPU. + +This is an asynchronous vcpu ioctl and can be invoked from any thread. + 4.17 KVM_DEBUG_GUEST -------------------- @@ -1364,7 +1381,7 @@ for vm-wide capabilities. --------------------- :Capability: KVM_CAP_MP_STATE -:Architectures: x86, s390, arm, arm64 +:Architectures: x86, s390, arm, arm64, riscv :Type: vcpu ioctl :Parameters: struct kvm_mp_state (out) :Returns: 0 on success; -1 on error @@ -1381,7 +1398,8 @@ uniprocessor guests). Possible values are: ========================== =============================================== - KVM_MP_STATE_RUNNABLE the vcpu is currently running [x86,arm/arm64] + KVM_MP_STATE_RUNNABLE the vcpu is currently running + [x86,arm/arm64,riscv] KVM_MP_STATE_UNINITIALIZED the vcpu is an application processor (AP) which has not yet received an INIT signal [x86] KVM_MP_STATE_INIT_RECEIVED the vcpu has received an INIT signal, and is @@ -1390,7 +1408,7 @@ Possible values are: is waiting for an interrupt [x86] KVM_MP_STATE_SIPI_RECEIVED the vcpu has just received a SIPI (vector accessible via KVM_GET_VCPU_EVENTS) [x86] - KVM_MP_STATE_STOPPED the vcpu is stopped [s390,arm/arm64] + KVM_MP_STATE_STOPPED the vcpu is stopped [s390,arm/arm64,riscv] KVM_MP_STATE_CHECK_STOP the vcpu is in a special error state [s390] KVM_MP_STATE_OPERATING the vcpu is operating (running or halted) [s390] @@ -1402,8 +1420,8 @@ On x86, this ioctl is only useful after KVM_CREATE_IRQCHIP. Without an in-kernel irqchip, the multiprocessing state must be maintained by userspace on these architectures. -For arm/arm64: -^^^^^^^^^^^^^^ +For arm/arm64/riscv: +^^^^^^^^^^^^^^^^^^^^ The only states that are valid are KVM_MP_STATE_STOPPED and KVM_MP_STATE_RUNNABLE which reflect if the vcpu is paused or not. @@ -1412,7 +1430,7 @@ KVM_MP_STATE_RUNNABLE which reflect if the vcpu is paused or not. --------------------- :Capability: KVM_CAP_MP_STATE -:Architectures: x86, s390, arm, arm64 +:Architectures: x86, s390, arm, arm64, riscv :Type: vcpu ioctl :Parameters: struct kvm_mp_state (in) :Returns: 0 on success; -1 on error @@ -1424,8 +1442,8 @@ On x86, this ioctl is only useful after KVM_CREATE_IRQCHIP. Without an in-kernel irqchip, the multiprocessing state must be maintained by userspace on these architectures. -For arm/arm64: -^^^^^^^^^^^^^^ +For arm/arm64/riscv: +^^^^^^^^^^^^^^^^^^^^ The only states that are valid are KVM_MP_STATE_STOPPED and KVM_MP_STATE_RUNNABLE which reflect if the vcpu should be paused or not. @@ -2539,6 +2557,144 @@ following id bit patterns:: 0x7020 0000 0003 02 <0:3> +RISC-V registers are mapped using the lower 32 bits. The upper 8 bits of +that is the register group type. + +RISC-V config registers are meant for configuring a Guest VCPU and it has +the following id bit patterns:: + + 0x8020 0000 01 (32bit Host) + 0x8030 0000 01 (64bit Host) + +Following are the RISC-V config registers: + +======================= ========= ============================================= + Encoding Register Description +======================= ========= ============================================= + 0x80x0 0000 0100 0000 isa ISA feature bitmap of Guest VCPU +======================= ========= ============================================= + +The isa config register can be read anytime but can only be written before +a Guest VCPU runs. It will have ISA feature bits matching underlying host +set by default. + +RISC-V core registers represent the general excution state of a Guest VCPU +and it has the following id bit patterns:: + + 0x8020 0000 02 (32bit Host) + 0x8030 0000 02 (64bit Host) + +Following are the RISC-V core registers: + +======================= ========= ============================================= + Encoding Register Description +======================= ========= ============================================= + 0x80x0 0000 0200 0000 regs.pc Program counter + 0x80x0 0000 0200 0001 regs.ra Return address + 0x80x0 0000 0200 0002 regs.sp Stack pointer + 0x80x0 0000 0200 0003 regs.gp Global pointer + 0x80x0 0000 0200 0004 regs.tp Task pointer + 0x80x0 0000 0200 0005 regs.t0 Caller saved register 0 + 0x80x0 0000 0200 0006 regs.t1 Caller saved register 1 + 0x80x0 0000 0200 0007 regs.t2 Caller saved register 2 + 0x80x0 0000 0200 0008 regs.s0 Callee saved register 0 + 0x80x0 0000 0200 0009 regs.s1 Callee saved register 1 + 0x80x0 0000 0200 000a regs.a0 Function argument (or return value) 0 + 0x80x0 0000 0200 000b regs.a1 Function argument (or return value) 1 + 0x80x0 0000 0200 000c regs.a2 Function argument 2 + 0x80x0 0000 0200 000d regs.a3 Function argument 3 + 0x80x0 0000 0200 000e regs.a4 Function argument 4 + 0x80x0 0000 0200 000f regs.a5 Function argument 5 + 0x80x0 0000 0200 0010 regs.a6 Function argument 6 + 0x80x0 0000 0200 0011 regs.a7 Function argument 7 + 0x80x0 0000 0200 0012 regs.s2 Callee saved register 2 + 0x80x0 0000 0200 0013 regs.s3 Callee saved register 3 + 0x80x0 0000 0200 0014 regs.s4 Callee saved register 4 + 0x80x0 0000 0200 0015 regs.s5 Callee saved register 5 + 0x80x0 0000 0200 0016 regs.s6 Callee saved register 6 + 0x80x0 0000 0200 0017 regs.s7 Callee saved register 7 + 0x80x0 0000 0200 0018 regs.s8 Callee saved register 8 + 0x80x0 0000 0200 0019 regs.s9 Callee saved register 9 + 0x80x0 0000 0200 001a regs.s10 Callee saved register 10 + 0x80x0 0000 0200 001b regs.s11 Callee saved register 11 + 0x80x0 0000 0200 001c regs.t3 Caller saved register 3 + 0x80x0 0000 0200 001d regs.t4 Caller saved register 4 + 0x80x0 0000 0200 001e regs.t5 Caller saved register 5 + 0x80x0 0000 0200 001f regs.t6 Caller saved register 6 + 0x80x0 0000 0200 0020 mode Privilege mode (1 = S-mode or 0 = U-mode) +======================= ========= ============================================= + +RISC-V csr registers represent the supervisor mode control/status registers +of a Guest VCPU and it has the following id bit patterns:: + + 0x8020 0000 03 (32bit Host) + 0x8030 0000 03 (64bit Host) + +Following are the RISC-V csr registers: + +======================= ========= ============================================= + Encoding Register Description +======================= ========= ============================================= + 0x80x0 0000 0300 0000 sstatus Supervisor status + 0x80x0 0000 0300 0001 sie Supervisor interrupt enable + 0x80x0 0000 0300 0002 stvec Supervisor trap vector base + 0x80x0 0000 0300 0003 sscratch Supervisor scratch register + 0x80x0 0000 0300 0004 sepc Supervisor exception program counter + 0x80x0 0000 0300 0005 scause Supervisor trap cause + 0x80x0 0000 0300 0006 stval Supervisor bad address or instruction + 0x80x0 0000 0300 0007 sip Supervisor interrupt pending + 0x80x0 0000 0300 0008 satp Supervisor address translation and protection +======================= ========= ============================================= + +RISC-V timer registers represent the timer state of a Guest VCPU and it has +the following id bit patterns:: + + 0x8030 0000 04 + +Following are the RISC-V timer registers: + +======================= ========= ============================================= + Encoding Register Description +======================= ========= ============================================= + 0x8030 0000 0400 0000 frequency Time base frequency (read-only) + 0x8030 0000 0400 0001 time Time value visible to Guest + 0x8030 0000 0400 0002 compare Time compare programmed by Guest + 0x8030 0000 0400 0003 state Time compare state (1 = ON or 0 = OFF) +======================= ========= ============================================= + +RISC-V F-extension registers represent the single precision floating point +state of a Guest VCPU and it has the following id bit patterns:: + + 0x8020 0000 05 + +Following are the RISC-V F-extension registers: + +======================= ========= ============================================= + Encoding Register Description +======================= ========= ============================================= + 0x8020 0000 0500 0000 f[0] Floating point register 0 + ... + 0x8020 0000 0500 001f f[31] Floating point register 31 + 0x8020 0000 0500 0020 fcsr Floating point control and status register +======================= ========= ============================================= + +RISC-V D-extension registers represent the double precision floating point +state of a Guest VCPU and it has the following id bit patterns:: + + 0x8020 0000 06 (fcsr) + 0x8030 0000 06 (non-fcsr) + +Following are the RISC-V D-extension registers: + +======================= ========= ============================================= + Encoding Register Description +======================= ========= ============================================= + 0x8030 0000 0600 0000 f[0] Floating point register 0 + ... + 0x8030 0000 0600 001f f[31] Floating point register 31 + 0x8020 0000 0600 0020 fcsr Floating point control and status register +======================= ========= ============================================= + 4.69 KVM_GET_ONE_REG -------------------- @@ -5163,6 +5319,25 @@ Note that KVM does not skip the faulting instruction as it does for KVM_EXIT_MMIO, but userspace has to emulate any change to the processing state if it decides to decode and emulate the instruction. +:: + + /* KVM_EXIT_RISCV_SBI */ + struct { + unsigned long extension_id; + unsigned long function_id; + unsigned long args[6]; + unsigned long ret[2]; + } riscv_sbi; +If exit reason is KVM_EXIT_RISCV_SBI then it indicates that the VCPU has +done a SBI call which is not handled by KVM RISC-V kernel module. The details +of the SBI call are available in 'riscv_sbi' member of kvm_run structure. The +'extension_id' field of 'riscv_sbi' represents SBI extension ID whereas the +'function_id' field represents function ID of given SBI extension. The 'args' +array field of 'riscv_sbi' represents parameters for the SBI call and 'ret' +array field represents return values. The userspace should update the return +values of SBI call before resuming the VCPU. For more details on RISC-V SBI +spec refer, https://github.com/riscv/riscv-sbi-doc. + :: /* Fix the size of the union. */