| Message ID | 20201203124703.168-4-jiangyifei@huawei.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Add riscv kvm accel support | expand |
On Thu, Dec 3, 2020 at 4:55 AM Yifei Jiang <jiangyifei@huawei.com> wrote: > > Get isa info from kvm while kvm init. > > Signed-off-by: Yifei Jiang <jiangyifei@huawei.com> > Signed-off-by: Yipeng Yin <yinyipeng1@huawei.com> > --- > target/riscv/kvm.c | 27 ++++++++++++++++++++++++++- > 1 file changed, 26 insertions(+), 1 deletion(-) > > diff --git a/target/riscv/kvm.c b/target/riscv/kvm.c > index 8c386d9acf..86660ba81b 100644 > --- a/target/riscv/kvm.c > +++ b/target/riscv/kvm.c > @@ -38,6 +38,18 @@ > #include "qemu/log.h" > #include "hw/loader.h" > > +static __u64 kvm_riscv_reg_id(__u64 type, __u64 idx) > +{ > + __u64 id = KVM_REG_RISCV | type | idx; > + > +#if defined(TARGET_RISCV32) > + id |= KVM_REG_SIZE_U32; > +#elif defined(TARGET_RISCV64) > + id |= KVM_REG_SIZE_U64; > +#endif There is a series on list (I'll send a v2 out later today) that starts to remove these #ifdef for the RISC-V XLEN. Next time you rebase it would be great if you can use that and hopefully remove this. Alistair > + return id; > +} > + > const KVMCapabilityInfo kvm_arch_required_capabilities[] = { > KVM_CAP_LAST_INFO > }; > @@ -79,7 +91,20 @@ void kvm_arch_init_irq_routing(KVMState *s) > > int kvm_arch_init_vcpu(CPUState *cs) > { > - return 0; > + int ret = 0; > + target_ulong isa; > + RISCVCPU *cpu = RISCV_CPU(cs); > + CPURISCVState *env = &cpu->env; > + __u64 id; > + > + id = kvm_riscv_reg_id(KVM_REG_RISCV_CONFIG, KVM_REG_RISCV_CONFIG_REG(isa)); > + ret = kvm_get_one_reg(cs, id, &isa); > + if (ret) { > + return ret; > + } > + env->misa = isa; > + > + return ret; > } > > int kvm_arch_msi_data_to_gsi(uint32_t data) > -- > 2.19.1 > >
diff --git a/target/riscv/kvm.c b/target/riscv/kvm.c index 8c386d9acf..86660ba81b 100644 --- a/target/riscv/kvm.c +++ b/target/riscv/kvm.c @@ -38,6 +38,18 @@ #include "qemu/log.h" #include "hw/loader.h" +static __u64 kvm_riscv_reg_id(__u64 type, __u64 idx) +{ + __u64 id = KVM_REG_RISCV | type | idx; + +#if defined(TARGET_RISCV32) + id |= KVM_REG_SIZE_U32; +#elif defined(TARGET_RISCV64) + id |= KVM_REG_SIZE_U64; +#endif + return id; +} + const KVMCapabilityInfo kvm_arch_required_capabilities[] = { KVM_CAP_LAST_INFO }; @@ -79,7 +91,20 @@ void kvm_arch_init_irq_routing(KVMState *s) int kvm_arch_init_vcpu(CPUState *cs) { - return 0; + int ret = 0; + target_ulong isa; + RISCVCPU *cpu = RISCV_CPU(cs); + CPURISCVState *env = &cpu->env; + __u64 id; + + id = kvm_riscv_reg_id(KVM_REG_RISCV_CONFIG, KVM_REG_RISCV_CONFIG_REG(isa)); + ret = kvm_get_one_reg(cs, id, &isa); + if (ret) { + return ret; + } + env->misa = isa; + + return ret; } int kvm_arch_msi_data_to_gsi(uint32_t data)