@@ -17,6 +17,7 @@
#define ARM64_WORKAROUND_834220 7
#define ARM64_HAS_NO_HW_PREFETCH 8
#define ARM64_HAS_NESTED_VIRT 9
+#define ARM64_HAS_ENHANCED_NESTED_VIRT 10
#define ARM64_HAS_VIRT_HOST_EXTN 11
#define ARM64_WORKAROUND_CAVIUM_27456 12
#define ARM64_HAS_32BIT_EL0 13
@@ -14,6 +14,12 @@ static inline bool nested_virt_in_use(const struct kvm_vcpu *vcpu)
test_bit(KVM_ARM_VCPU_HAS_EL2, vcpu->arch.features));
}
+static inline bool enhanced_nested_virt_in_use(const struct kvm_vcpu *vcpu)
+{
+ return cpus_have_final_cap(ARM64_HAS_ENHANCED_NESTED_VIRT) &&
+ nested_virt_in_use(vcpu);
+}
+
/* Translation helpers from non-VHE EL2 to EL1 */
static inline u64 tcr_el2_ips_to_tcr_el1_ps(u64 tcr_el2)
{
@@ -1815,6 +1815,16 @@ static const struct arm64_cpu_capabilities arm64_features[] = {
.field_pos = ID_AA64MMFR2_NV_SHIFT,
.min_field_value = 1,
},
+ {
+ .desc = "Enhanced Nested Virtualization Support",
+ .capability = ARM64_HAS_ENHANCED_NESTED_VIRT,
+ .type = ARM64_CPUCAP_SYSTEM_FEATURE,
+ .matches = has_nested_virt_support,
+ .sys_reg = SYS_ID_AA64MMFR2_EL1,
+ .sign = FTR_UNSIGNED,
+ .field_pos = ID_AA64MMFR2_NV_SHIFT,
+ .min_field_value = 2,
+ },
#endif /* CONFIG_ARM64_VHE */
{
.desc = "32-bit EL0 Support",
Add the detection code for the ARMv8.4-NV feature. Signed-off-by: Marc Zyngier <maz@kernel.org> --- arch/arm64/include/asm/cpucaps.h | 1 + arch/arm64/include/asm/kvm_nested.h | 6 ++++++ arch/arm64/kernel/cpufeature.c | 10 ++++++++++ 3 files changed, 17 insertions(+)