diff mbox series

[3/3] KVM/VMX: Use try_cmpxchg64() in posted_intr.c

Message ID 20201215182805.53913-4-ubizjak@gmail.com (mailing list archive)
State New, archived
Headers show
Series x86/KVM/VMX: Introduce and use try_cmpxchg64() | expand

Commit Message

Uros Bizjak Dec. 15, 2020, 6:28 p.m. UTC 
Use try_cmpxchg64() instead of cmpxchg64() to reuse flags from
cmpxchg/cmpxchg8b instruction. For 64 bit targets flags reuse
avoids a CMP instruction, while for 32 bit targets flags reuse
avoids XOR/XOR/OR instruction sequence.

Signed-off-by: Uros Bizjak <ubizjak@gmail.com>
Cc: Paolo Bonzini <pbonzini@redhat.com>
Cc: Sean Christopherson <seanjc@google.com>
Cc: Vitaly Kuznetsov <vkuznets@redhat.com>
Cc: Wanpeng Li <wanpengli@tencent.com>
Cc: Jim Mattson <jmattson@google.com>
Cc: Joerg Roedel <joro@8bytes.org>
---
 arch/x86/kvm/vmx/posted_intr.c | 9 +++------
 1 file changed, 3 insertions(+), 6 deletions(-)

Comments

Sean Christopherson Jan. 15, 2021, 7:28 p.m. UTC | #1 
On Tue, Dec 15, 2020, Uros Bizjak wrote:
> Use try_cmpxchg64() instead of cmpxchg64() to reuse flags from
> cmpxchg/cmpxchg8b instruction. For 64 bit targets flags reuse
> avoids a CMP instruction,

It ends up doing way more (in a good way) than eliminate the CMP, at least with
gcc-10.  There's a ripple effect and the compiler ends up generating the loop
in-line, whereas without the "try" version the loop is put out-of-line.

> while for 32 bit targets flags reuse avoids XOR/XOR/OR instruction sequence.
> 
> Signed-off-by: Uros Bizjak <ubizjak@gmail.com>

Reviewed-by: Sean Christopherson <seanjc@google.com>
diff mbox series

Patch

diff --git a/arch/x86/kvm/vmx/posted_intr.c b/arch/x86/kvm/vmx/posted_intr.c
index f02962dcc72c..47b47970fb46 100644
--- a/arch/x86/kvm/vmx/posted_intr.c
+++ b/arch/x86/kvm/vmx/posted_intr.c
@@ -60,8 +60,7 @@  void vmx_vcpu_pi_load(struct kvm_vcpu *vcpu, int cpu)
 			new.ndst = (dest << 8) & 0xFF00;
 
 		new.sn = 0;
-	} while (cmpxchg64(&pi_desc->control, old.control,
-			   new.control) != old.control);
+	} while (!try_cmpxchg64(&pi_desc->control, &old.control, new.control));
 
 after_clear_sn:
 
@@ -111,8 +110,7 @@  static void __pi_post_block(struct kvm_vcpu *vcpu)
 
 		/* set 'NV' to 'notification vector' */
 		new.nv = POSTED_INTR_VECTOR;
-	} while (cmpxchg64(&pi_desc->control, old.control,
-			   new.control) != old.control);
+	} while (!try_cmpxchg64(&pi_desc->control, &old.control, new.control));
 
 	if (!WARN_ON_ONCE(vcpu->pre_pcpu == -1)) {
 		spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock, vcpu->pre_pcpu));
@@ -181,8 +179,7 @@  int pi_pre_block(struct kvm_vcpu *vcpu)
 
 		/* set 'NV' to 'wakeup vector' */
 		new.nv = POSTED_INTR_WAKEUP_VECTOR;
-	} while (cmpxchg64(&pi_desc->control, old.control,
-			   new.control) != old.control);
+	} while (!try_cmpxchg64(&pi_desc->control, &old.control, new.control));
 
 	/* We should not block the vCPU if an interrupt is posted for it.  */
 	if (pi_test_on(pi_desc) == 1)