[PULL,04/66] target/mips/mips-defs: Remove USE_HOST_FLOAT_REGS comment

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From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= <f4bug@amsat.org>
To: qemu-devel@nongnu.org
Cc: libvir-list@redhat.com, Paolo Bonzini <pbonzini@redhat.com>,
 Laurent Vivier <laurent@vivier.eu>, kvm@vger.kernel.org,
 Jiaxun Yang <jiaxun.yang@flygoat.com>, Aurelien Jarno <aurelien@aurel32.net>,
 Huacai Chen <chenhuacai@kernel.org>,
 =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= <f4bug@amsat.org>,
 Aleksandar Rikalo <aleksandar.rikalo@syrmia.com>,
 Paul Burton <paulburton@kernel.org>,
 Richard Henderson <richard.henderson@linaro.org>
Subject: [PULL 04/66] target/mips/mips-defs: Remove USE_HOST_FLOAT_REGS
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Date: Thu,  7 Jan 2021 23:21:51 +0100
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Message ID	20210107222253.20382-5-f4bug@amsat.org (mailing list archive)
State	New, archived
Headers	show Return-Path: <kvm-owner@kernel.org> Sender: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= <philippe.mathieu.daude@gmail.com> From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= <f4bug@amsat.org> To: qemu-devel@nongnu.org Cc: libvir-list@redhat.com, Paolo Bonzini <pbonzini@redhat.com>, Laurent Vivier <laurent@vivier.eu>, kvm@vger.kernel.org, Jiaxun Yang <jiaxun.yang@flygoat.com>, Aurelien Jarno <aurelien@aurel32.net>, Huacai Chen <chenhuacai@kernel.org>, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= <f4bug@amsat.org>, Aleksandar Rikalo <aleksandar.rikalo@syrmia.com>, Paul Burton <paulburton@kernel.org>, Richard Henderson <richard.henderson@linaro.org> Subject: [PULL 04/66] target/mips/mips-defs: Remove USE_HOST_FLOAT_REGS comment Date: Thu, 7 Jan 2021 23:21:51 +0100 Message-Id: <20210107222253.20382-5-f4bug@amsat.org> In-Reply-To: <20210107222253.20382-1-f4bug@amsat.org> References: <20210107222253.20382-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Precedence: bulk
Series	[PULL,01/66] target/mips: Add CP0 Config0 register definitions for MIPS3 ISA \| expand [PULL,01/66] target/mips: Add CP0 Config0 register definitions for MIPS3 ISA [PULL,02/66] target/mips: Replace CP0_Config0 magic values by proper definitions [PULL,03/66] target/mips/addr: Add translation helpers for KSEG1 [PULL,04/66] target/mips/mips-defs: Remove USE_HOST_FLOAT_REGS comment [PULL,05/66] target/mips/mips-defs: Reorder CPU_MIPS5 definition [PULL,06/66] target/mips/mips-defs: Rename CPU_MIPSxx Release 1 as CPU_MIPSxxR1 [PULL,07/66] target/mips/mips-defs: Introduce CPU_MIPS64 and cpu_type_is_64bit() [PULL,08/66] hw/mips/boston: Check 64-bit support with cpu_type_is_64bit() [PULL,09/66] target/mips/mips-defs: Use ISA_MIPS32 definition to check Release 1 [PULL,10/66] target/mips/mips-defs: Use ISA_MIPS32R2 definition to check Release 2 [PULL,11/66] target/mips/mips-defs: Use ISA_MIPS32R3 definition to check Release 3 [PULL,12/66] target/mips/mips-defs: Use ISA_MIPS32R5 definition to check Release 5 [PULL,13/66] target/mips/mips-defs: Use ISA_MIPS32R6 definition to check Release 6 [PULL,14/66] target/mips/mips-defs: Rename ISA_MIPS32 as ISA_MIPS_R1 [PULL,15/66] target/mips/mips-defs: Rename ISA_MIPS32R2 as ISA_MIPS_R2 [PULL,16/66] target/mips/mips-defs: Rename ISA_MIPS32R3 as ISA_MIPS_R3 [PULL,17/66] target/mips/mips-defs: Rename ISA_MIPS32R5 as ISA_MIPS_R5 [PULL,18/66] target/mips/mips-defs: Rename ISA_MIPS32R6 as ISA_MIPS_R6 [PULL,19/66] target/mips: Inline cpu_state_reset() in mips_cpu_reset() [PULL,20/66] target/mips: Extract FPU helpers to 'fpu_helper.h' [PULL,21/66] target/mips: Add !CONFIG_USER_ONLY comment after #endif [PULL,22/66] target/mips: Remove consecutive CONFIG_USER_ONLY ifdefs [PULL,23/66] target/mips: Move common helpers from helper.c to cpu.c [PULL,24/66] target/mips: Rename helper.c as tlb_helper.c [PULL,25/66] target/mips: Fix code style for checkpatch.pl [PULL,26/66] target/mips: Move mmu_init() functions to tlb_helper.c [PULL,27/66] target/mips: Rename translate_init.c as cpu-defs.c [PULL,28/66] target/mips/translate: Extract DisasContext structure [PULL,29/66] target/mips/translate: Add declarations for generic code [PULL,30/66] target/mips: Replace gen_exception_err(err=0) by gen_exception_end() [PULL,32/66] target/mips: Declare generic FPU functions in 'translate.h' [PULL,33/66] target/mips: Extract FPU specific definitions to translate.h [PULL,34/66] target/mips: Only build TCG code when CONFIG_TCG is set [PULL,35/66] target/mips/translate: Extract decode_opc_legacy() from decode_opc() [PULL,36/66] target/mips/translate: Expose check_mips_64() to 32-bit mode [PULL,37/66] target/mips: Introduce ase_msa_available() helper [PULL,38/66] target/mips: Simplify msa_reset() [PULL,39/66] target/mips: Use CP0_Config3 to set MIPS_HFLAG_MSA [PULL,40/66] target/mips: Simplify MSA TCG logic [PULL,41/66] target/mips: Remove now unused ASE_MSA definition [PULL,42/66] target/mips: Alias MSA vector registers on FPU scalar registers [PULL,43/66] target/mips: Extract msa_translate_init() from mips_tcg_init() [PULL,44/66] target/mips: Remove CPUMIPSState* argument from gen_msa*() methods [PULL,45/66] target/mips: Explode gen_msa_branch() as gen_msa_BxZ_V/BxZ() [PULL,46/66] target/mips: Move msa_reset() to msa_helper.c [PULL,47/66] target/mips: Extract MSA helpers from op_helper.c [PULL,48/66] target/mips: Extract MSA helper definitions [PULL,49/66] target/mips: Declare gen_msa/_branch() in 'translate.h' [PULL,51/66] target/mips: Pass TCGCond argument to MSA gen_check_zero_element() [PULL,52/66] target/mips: Introduce decode tree bindings for MSA ASE [PULL,53/66] target/mips: Use decode_ase_msa() generated from decodetree [PULL,54/66] target/mips: Extract LSA/DLSA translation generators [PULL,55/66] target/mips: Introduce decodetree helpers for MSA LSA/DLSA opcodes [PULL,56/66] target/mips: Introduce decodetree helpers for Release6 LSA/DLSA opcodes [PULL,57/66] target/mips: Remove now unreachable LSA/DLSA opcodes code [PULL,58/66] target/mips: Convert Rel6 Special2 opcode to decodetree [PULL,59/66] target/mips: Convert Rel6 COP1X opcode to decodetree [PULL,60/66] target/mips: Convert Rel6 CACHE/PREF opcodes to decodetree [PULL,61/66] target/mips: Convert Rel6 LWL/LWR/SWL/SWR opcodes to decodetree [PULL,62/66] target/mips: Convert Rel6 LWLE/LWRE/SWLE/SWRE opcodes to decodetree [PULL,63/66] target/mips: Convert Rel6 LDL/LDR/SDL/SDR opcodes to decodetree [PULL,64/66] target/mips: Convert Rel6 LLD/SCD opcodes to decodetree [PULL,65/66] target/mips: Convert Rel6 LL/SC opcodes to decodetree [PULL,66/66] docs/system: Remove deprecated 'fulong2e' machine alias

[PULL,04/66] target/mips/mips-defs: Remove USE_HOST_FLOAT_REGS comment

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