diff mbox series

KVM: nVMX: Set X86_CR4_CET in cr4_fixed1_bits if CET IBT is enabled

Message ID 20210225030951.17099-1-weijiang.yang@intel.com (mailing list archive)
State New, archived
Headers show
Series KVM: nVMX: Set X86_CR4_CET in cr4_fixed1_bits if CET IBT is enabled | expand

Commit Message

Yang Weijiang Feb. 25, 2021, 3:09 a.m. UTC
CET SHSTK and IBT are independently controlled by kernel, set X86_CR4_CET
bit in cr4_fixed1_bits if either of them is enabled so that nested guest
can enjoy the feature.

Signed-off-by: Yang Weijiang <weijiang.yang@intel.com>
---
 arch/x86/kvm/vmx/vmx.c | 1 +
 1 file changed, 1 insertion(+)

Comments

Sean Christopherson March 1, 2021, 5:39 p.m. UTC | #1
On Thu, Feb 25, 2021, Yang Weijiang wrote:
> CET SHSTK and IBT are independently controlled by kernel, set X86_CR4_CET
> bit in cr4_fixed1_bits if either of them is enabled so that nested guest
> can enjoy the feature.
> 
> Signed-off-by: Yang Weijiang <weijiang.yang@intel.com>
> ---
>  arch/x86/kvm/vmx/vmx.c | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/arch/x86/kvm/vmx/vmx.c b/arch/x86/kvm/vmx/vmx.c
> index 5856c5b81084..e92134ee081c 100644
> --- a/arch/x86/kvm/vmx/vmx.c
> +++ b/arch/x86/kvm/vmx/vmx.c
> @@ -7258,6 +7258,7 @@ static void nested_vmx_cr_fixed1_bits_update(struct kvm_vcpu *vcpu)
>  	cr4_fixed1_update(X86_CR4_UMIP,       ecx, feature_bit(UMIP));
>  	cr4_fixed1_update(X86_CR4_LA57,       ecx, feature_bit(LA57));
>  	cr4_fixed1_update(X86_CR4_CET,	      ecx, feature_bit(SHSTK));
> +	cr4_fixed1_update(X86_CR4_CET,	      edx, feature_bit(IBT));

Ugh, what sadist put SHSTK and IBT in separate output registers.

Reviewed-by: Sean Christopherson <seanjc@google.com>

>  
>  #undef cr4_fixed1_update
>  }
> -- 
> 2.26.2
>
diff mbox series

Patch

diff --git a/arch/x86/kvm/vmx/vmx.c b/arch/x86/kvm/vmx/vmx.c
index 5856c5b81084..e92134ee081c 100644
--- a/arch/x86/kvm/vmx/vmx.c
+++ b/arch/x86/kvm/vmx/vmx.c
@@ -7258,6 +7258,7 @@  static void nested_vmx_cr_fixed1_bits_update(struct kvm_vcpu *vcpu)
 	cr4_fixed1_update(X86_CR4_UMIP,       ecx, feature_bit(UMIP));
 	cr4_fixed1_update(X86_CR4_LA57,       ecx, feature_bit(LA57));
 	cr4_fixed1_update(X86_CR4_CET,	      ecx, feature_bit(SHSTK));
+	cr4_fixed1_update(X86_CR4_CET,	      edx, feature_bit(IBT));
 
 #undef cr4_fixed1_update
 }