| Message ID | 20210303135756.1546253-4-like.xu@linux.intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | KVM: x86/pmu: Guest Architectural LBR Enabling | expand |
diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c index a32acc7733a7..3cf065185fb0 100644 --- a/arch/x86/events/intel/core.c +++ b/arch/x86/events/intel/core.c @@ -5569,7 +5569,8 @@ __init int intel_pmu_init(void) * Check all LBT MSR here. * Disable LBR access if any LBR MSRs can not be accessed. */ - if (x86_pmu.lbr_nr && !check_msr(x86_pmu.lbr_tos, 0x3UL)) + if (x86_pmu.lbr_nr && !boot_cpu_has(X86_FEATURE_ARCH_LBR) && + !check_msr(x86_pmu.lbr_tos, 0x3UL)) x86_pmu.lbr_nr = 0; for (i = 0; i < x86_pmu.lbr_nr; i++) { if (!(check_msr(x86_pmu.lbr_from + i, 0xffffUL) &&
The Architecture LBR does not have MSR_LBR_TOS (0x000001c9). KVM will generate #GP for this MSR access, thereby preventing the initialization of the guest LBR. Cc: Peter Zijlstra <peterz@infradead.org> Fixes: 47125db27e47 ("perf/x86/intel/lbr: Support Architectural LBR") Signed-off-by: Like Xu <like.xu@linux.intel.com> Reviewed-by: Kan Liang <kan.liang@linux.intel.com> --- arch/x86/events/intel/core.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-)