| Message ID | 20210330095350.36309-3-ravi.bangoria@linux.ibm.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | ppc: Enable 2nd DAWR support on Power10 | expand |
On Tue, 30 Mar 2021 15:23:49 +0530 Ravi Bangoria <ravi.bangoria@linux.ibm.com> wrote: > Power10 is introducing second DAWR. Use real register names (with > suffix 0) from ISA for current macros and variables used by Qemu. > > One exception to this is KVM_REG_PPC_DAWR[X]. This is from kernel > uapi header and thus not changed in kernel as well as Qemu. > > Signed-off-by: Ravi Bangoria <ravi.bangoria@linux.ibm.com> > --- Reviewed-by: Greg Kurz <groug@kaod.org> > include/hw/ppc/spapr.h | 2 +- > target/ppc/cpu.h | 4 ++-- > target/ppc/translate_init.c.inc | 4 ++-- > 3 files changed, 5 insertions(+), 5 deletions(-) > > diff --git a/include/hw/ppc/spapr.h b/include/hw/ppc/spapr.h > index 47cebaf3ac..b8985fab5b 100644 > --- a/include/hw/ppc/spapr.h > +++ b/include/hw/ppc/spapr.h > @@ -363,7 +363,7 @@ struct SpaprMachineState { > > /* Values for 2nd argument to H_SET_MODE */ > #define H_SET_MODE_RESOURCE_SET_CIABR 1 > -#define H_SET_MODE_RESOURCE_SET_DAWR 2 > +#define H_SET_MODE_RESOURCE_SET_DAWR0 2 > #define H_SET_MODE_RESOURCE_ADDR_TRANS_MODE 3 > #define H_SET_MODE_RESOURCE_LE 4 > > diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h > index e73416da68..cd02d65303 100644 > --- a/target/ppc/cpu.h > +++ b/target/ppc/cpu.h > @@ -1459,10 +1459,10 @@ typedef PowerPCCPU ArchCPU; > #define SPR_MPC_BAR (0x09F) > #define SPR_PSPB (0x09F) > #define SPR_DPDES (0x0B0) > -#define SPR_DAWR (0x0B4) > +#define SPR_DAWR0 (0x0B4) > #define SPR_RPR (0x0BA) > #define SPR_CIABR (0x0BB) > -#define SPR_DAWRX (0x0BC) > +#define SPR_DAWRX0 (0x0BC) > #define SPR_HFSCR (0x0BE) > #define SPR_VRSAVE (0x100) > #define SPR_USPRG0 (0x100) > diff --git a/target/ppc/translate_init.c.inc b/target/ppc/translate_init.c.inc > index c03a7c4f52..879e6df217 100644 > --- a/target/ppc/translate_init.c.inc > +++ b/target/ppc/translate_init.c.inc > @@ -7748,12 +7748,12 @@ static void gen_spr_book3s_dbg(CPUPPCState *env) > > static void gen_spr_book3s_207_dbg(CPUPPCState *env) > { > - spr_register_kvm_hv(env, SPR_DAWR, "DAWR", > + spr_register_kvm_hv(env, SPR_DAWR0, "DAWR0", > SPR_NOACCESS, SPR_NOACCESS, > SPR_NOACCESS, SPR_NOACCESS, > &spr_read_generic, &spr_write_generic, > KVM_REG_PPC_DAWR, 0x00000000); > - spr_register_kvm_hv(env, SPR_DAWRX, "DAWRX", > + spr_register_kvm_hv(env, SPR_DAWRX0, "DAWRX0", > SPR_NOACCESS, SPR_NOACCESS, > SPR_NOACCESS, SPR_NOACCESS, > &spr_read_generic, &spr_write_generic,
On Tue, Mar 30, 2021 at 03:23:49PM +0530, Ravi Bangoria wrote: > Power10 is introducing second DAWR. Use real register names (with > suffix 0) from ISA for current macros and variables used by Qemu. > > One exception to this is KVM_REG_PPC_DAWR[X]. This is from kernel > uapi header and thus not changed in kernel as well as Qemu. > > Signed-off-by: Ravi Bangoria <ravi.bangoria@linux.ibm.com> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> > --- > include/hw/ppc/spapr.h | 2 +- > target/ppc/cpu.h | 4 ++-- > target/ppc/translate_init.c.inc | 4 ++-- > 3 files changed, 5 insertions(+), 5 deletions(-) > > diff --git a/include/hw/ppc/spapr.h b/include/hw/ppc/spapr.h > index 47cebaf3ac..b8985fab5b 100644 > --- a/include/hw/ppc/spapr.h > +++ b/include/hw/ppc/spapr.h > @@ -363,7 +363,7 @@ struct SpaprMachineState { > > /* Values for 2nd argument to H_SET_MODE */ > #define H_SET_MODE_RESOURCE_SET_CIABR 1 > -#define H_SET_MODE_RESOURCE_SET_DAWR 2 > +#define H_SET_MODE_RESOURCE_SET_DAWR0 2 > #define H_SET_MODE_RESOURCE_ADDR_TRANS_MODE 3 > #define H_SET_MODE_RESOURCE_LE 4 > > diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h > index e73416da68..cd02d65303 100644 > --- a/target/ppc/cpu.h > +++ b/target/ppc/cpu.h > @@ -1459,10 +1459,10 @@ typedef PowerPCCPU ArchCPU; > #define SPR_MPC_BAR (0x09F) > #define SPR_PSPB (0x09F) > #define SPR_DPDES (0x0B0) > -#define SPR_DAWR (0x0B4) > +#define SPR_DAWR0 (0x0B4) > #define SPR_RPR (0x0BA) > #define SPR_CIABR (0x0BB) > -#define SPR_DAWRX (0x0BC) > +#define SPR_DAWRX0 (0x0BC) > #define SPR_HFSCR (0x0BE) > #define SPR_VRSAVE (0x100) > #define SPR_USPRG0 (0x100) > diff --git a/target/ppc/translate_init.c.inc b/target/ppc/translate_init.c.inc > index c03a7c4f52..879e6df217 100644 > --- a/target/ppc/translate_init.c.inc > +++ b/target/ppc/translate_init.c.inc > @@ -7748,12 +7748,12 @@ static void gen_spr_book3s_dbg(CPUPPCState *env) > > static void gen_spr_book3s_207_dbg(CPUPPCState *env) > { > - spr_register_kvm_hv(env, SPR_DAWR, "DAWR", > + spr_register_kvm_hv(env, SPR_DAWR0, "DAWR0", > SPR_NOACCESS, SPR_NOACCESS, > SPR_NOACCESS, SPR_NOACCESS, > &spr_read_generic, &spr_write_generic, > KVM_REG_PPC_DAWR, 0x00000000); > - spr_register_kvm_hv(env, SPR_DAWRX, "DAWRX", > + spr_register_kvm_hv(env, SPR_DAWRX0, "DAWRX0", > SPR_NOACCESS, SPR_NOACCESS, > SPR_NOACCESS, SPR_NOACCESS, > &spr_read_generic, &spr_write_generic,
diff --git a/include/hw/ppc/spapr.h b/include/hw/ppc/spapr.h index 47cebaf3ac..b8985fab5b 100644 --- a/include/hw/ppc/spapr.h +++ b/include/hw/ppc/spapr.h @@ -363,7 +363,7 @@ struct SpaprMachineState { /* Values for 2nd argument to H_SET_MODE */ #define H_SET_MODE_RESOURCE_SET_CIABR 1 -#define H_SET_MODE_RESOURCE_SET_DAWR 2 +#define H_SET_MODE_RESOURCE_SET_DAWR0 2 #define H_SET_MODE_RESOURCE_ADDR_TRANS_MODE 3 #define H_SET_MODE_RESOURCE_LE 4 diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index e73416da68..cd02d65303 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -1459,10 +1459,10 @@ typedef PowerPCCPU ArchCPU; #define SPR_MPC_BAR (0x09F) #define SPR_PSPB (0x09F) #define SPR_DPDES (0x0B0) -#define SPR_DAWR (0x0B4) +#define SPR_DAWR0 (0x0B4) #define SPR_RPR (0x0BA) #define SPR_CIABR (0x0BB) -#define SPR_DAWRX (0x0BC) +#define SPR_DAWRX0 (0x0BC) #define SPR_HFSCR (0x0BE) #define SPR_VRSAVE (0x100) #define SPR_USPRG0 (0x100) diff --git a/target/ppc/translate_init.c.inc b/target/ppc/translate_init.c.inc index c03a7c4f52..879e6df217 100644 --- a/target/ppc/translate_init.c.inc +++ b/target/ppc/translate_init.c.inc @@ -7748,12 +7748,12 @@ static void gen_spr_book3s_dbg(CPUPPCState *env) static void gen_spr_book3s_207_dbg(CPUPPCState *env) { - spr_register_kvm_hv(env, SPR_DAWR, "DAWR", + spr_register_kvm_hv(env, SPR_DAWR0, "DAWR0", SPR_NOACCESS, SPR_NOACCESS, SPR_NOACCESS, SPR_NOACCESS, &spr_read_generic, &spr_write_generic, KVM_REG_PPC_DAWR, 0x00000000); - spr_register_kvm_hv(env, SPR_DAWRX, "DAWRX", + spr_register_kvm_hv(env, SPR_DAWRX0, "DAWRX0", SPR_NOACCESS, SPR_NOACCESS, SPR_NOACCESS, SPR_NOACCESS, &spr_read_generic, &spr_write_generic,
Power10 is introducing second DAWR. Use real register names (with suffix 0) from ISA for current macros and variables used by Qemu. One exception to this is KVM_REG_PPC_DAWR[X]. This is from kernel uapi header and thus not changed in kernel as well as Qemu. Signed-off-by: Ravi Bangoria <ravi.bangoria@linux.ibm.com> --- include/hw/ppc/spapr.h | 2 +- target/ppc/cpu.h | 4 ++-- target/ppc/translate_init.c.inc | 4 ++-- 3 files changed, 5 insertions(+), 5 deletions(-)