| Message ID | 20210609182945.36849-8-nadav.amit@gmail.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | x86: non-KVM improvements | expand |
Hi Nadav, Nadav Amit <nadav.amit@gmail.com> 于2021年6月10日周四 上午2:33写道： > > From: Nadav Amit <nadav.amit@gmail.com> > > x86's PMU tests are not compatible with version 1. Instead of finding > how to adapt them, just skip them if the PMU version is too old. Instead of skipping pmu.v1, it would be better to just skip the tests of fixed counters. But considering this version is really too old, this change looks fine to me. > > Signed-off-by: Nadav Amit <nadav.amit@gmail.com> > --- > x86/pmu.c | 6 ++++++ > 1 file changed, 6 insertions(+) > > diff --git a/x86/pmu.c b/x86/pmu.c > index 5a3d55b..ec61ac9 100644 > --- a/x86/pmu.c > +++ b/x86/pmu.c > @@ -544,6 +544,12 @@ int main(int ac, char **av) > printf("No pmu is detected!\n"); > return report_summary(); > } > + > + if (eax.split.version_id == 1) { > + printf("PMU version 1 is not supported\n"); > + return report_summary(); > + } > + > printf("PMU version: %d\n", eax.split.version_id); > printf("GP counters: %d\n", eax.split.num_counters); > printf("GP counter width: %d\n", eax.split.bit_width); > -- > 2.25.1 >
> On Jun 9, 2021, at 6:22 PM, Like Xu <like.xu.linux@gmail.com> wrote: > > Hi Nadav, > > Nadav Amit <nadav.amit@gmail.com> 于2021年6月10日周四 上午2:33写道： >> >> From: Nadav Amit <nadav.amit@gmail.com> >> >> x86's PMU tests are not compatible with version 1. Instead of finding >> how to adapt them, just skip them if the PMU version is too old. > > Instead of skipping pmu.v1, it would be better to just skip the tests > of fixed counters. > But considering this version is really too old, this change looks fine to me. If it were that simple, I would have done it. v1 does not support MSR_CORE_PERF_GLOBAL_OVF_CTRL, MSR_CORE_PERF_GLOBAL_STATUS and MSR_CORE_PERF_GLOBAL_CTRL, which are being used all over the code. These MSRs were only introduced on version 2 (Intel SDM, section 18.2.2 "Architectural Performance Monitoring Version 2”).
On Thu, Jun 10, 2021 at 3:44 PM Nadav Amit <nadav.amit@gmail.com> wrote: > > > > > On Jun 9, 2021, at 6:22 PM, Like Xu <like.xu.linux@gmail.com> wrote: > > > > Hi Nadav, > > > > Nadav Amit <nadav.amit@gmail.com> 于2021年6月10日周四 上午2:33写道： > >> > >> From: Nadav Amit <nadav.amit@gmail.com> > >> > >> x86's PMU tests are not compatible with version 1. Instead of finding > >> how to adapt them, just skip them if the PMU version is too old. > > > > Instead of skipping pmu.v1, it would be better to just skip the tests > > of fixed counters. > > But considering this version is really too old, this change looks fine to me. > > If it were that simple, I would have done it. > > v1 does not support MSR_CORE_PERF_GLOBAL_OVF_CTRL, > MSR_CORE_PERF_GLOBAL_STATUS and MSR_CORE_PERF_GLOBAL_CTRL, which are > being used all over the code. These MSRs were only introduced on > version 2 (Intel SDM, section 18.2.2 "Architectural Performance > Monitoring Version 2”). > From the log of feature enbling code, this is true. But accroding to Table 2-2. IA-32 Architectural MSRs, - IA32_PERF_GLOBAL_OVF_CTRL, if CPUID.0AH: EAX[7:0] > 0 && CPUID.0AH: EAX[7:0] <= 3 - IA32_PERF_GLOBAL_STATUS, if CPUID.0AH: EAX[7:0] > 0 - IA32_PERF_GLOBAL_CTRL, if CPUID.0AH: EAX[7:0] > 0
diff --git a/x86/pmu.c b/x86/pmu.c index 5a3d55b..ec61ac9 100644 --- a/x86/pmu.c +++ b/x86/pmu.c @@ -544,6 +544,12 @@ int main(int ac, char **av) printf("No pmu is detected!\n"); return report_summary(); } + + if (eax.split.version_id == 1) { + printf("PMU version 1 is not supported\n"); + return report_summary(); + } + printf("PMU version: %d\n", eax.split.version_id); printf("GP counters: %d\n", eax.split.num_counters); printf("GP counter width: %d\n", eax.split.bit_width);