Message ID | 20210622094306.8336-12-lingshan.zhu@intel.com (mailing list archive) |
---|---|
State | New, archived |
Headers | show |
Series | KVM: x86/pmu: Add *basic* support to enable guest PEBS via DS | expand |
On Tue, Jun 22, 2021 at 05:42:59PM +0800, Zhu Lingshan wrote: > diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c > index 190d8d98abf0..b336bcaad626 100644 > --- a/arch/x86/events/intel/core.c > +++ b/arch/x86/events/intel/core.c > @@ -21,6 +21,7 @@ > #include <asm/intel_pt.h> > #include <asm/apic.h> > #include <asm/cpu_device_id.h> > +#include <asm/kvm_host.h> > > #include "../perf_event.h" > > @@ -3915,6 +3916,7 @@ static struct perf_guest_switch_msr *intel_guest_get_msrs(int *nr, void *data) > { > struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); > struct perf_guest_switch_msr *arr = cpuc->guest_switch_msrs; > + struct kvm_pmu *pmu = (struct kvm_pmu *)data; > u64 intel_ctrl = hybrid(cpuc->pmu, intel_ctrl); > u64 pebs_mask = cpuc->pebs_enabled & x86_pmu.pebs_capable; > > @@ -3945,9 +3947,15 @@ static struct perf_guest_switch_msr *intel_guest_get_msrs(int *nr, void *data) > return arr; > } > > - if (!x86_pmu.pebs_vmx) > + if (!pmu || !x86_pmu.pebs_vmx) > return arr; > > + arr[(*nr)++] = (struct perf_guest_switch_msr){ > + .msr = MSR_IA32_DS_AREA, > + .host = (unsigned long)cpuc->ds, > + .guest = pmu->ds_area, > + }; > + > arr[*nr] = (struct perf_guest_switch_msr){ > .msr = MSR_IA32_PEBS_ENABLE, > .host = cpuc->pebs_enabled & ~cpuc->intel_ctrl_guest_mask, s/pmu/kvm_pmu/ or something. pmu is normally a struct pmu *, and having it be kvm_pmu here is super confusing.
On 7/2/2021 7:52 PM, Peter Zijlstra wrote: > On Tue, Jun 22, 2021 at 05:42:59PM +0800, Zhu Lingshan wrote: >> diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c >> index 190d8d98abf0..b336bcaad626 100644 >> --- a/arch/x86/events/intel/core.c >> +++ b/arch/x86/events/intel/core.c >> @@ -21,6 +21,7 @@ >> #include <asm/intel_pt.h> >> #include <asm/apic.h> >> #include <asm/cpu_device_id.h> >> +#include <asm/kvm_host.h> >> >> #include "../perf_event.h" >> >> @@ -3915,6 +3916,7 @@ static struct perf_guest_switch_msr *intel_guest_get_msrs(int *nr, void *data) >> { >> struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); >> struct perf_guest_switch_msr *arr = cpuc->guest_switch_msrs; >> + struct kvm_pmu *pmu = (struct kvm_pmu *)data; >> u64 intel_ctrl = hybrid(cpuc->pmu, intel_ctrl); >> u64 pebs_mask = cpuc->pebs_enabled & x86_pmu.pebs_capable; >> >> @@ -3945,9 +3947,15 @@ static struct perf_guest_switch_msr *intel_guest_get_msrs(int *nr, void *data) >> return arr; >> } >> >> - if (!x86_pmu.pebs_vmx) >> + if (!pmu || !x86_pmu.pebs_vmx) >> return arr; >> >> + arr[(*nr)++] = (struct perf_guest_switch_msr){ >> + .msr = MSR_IA32_DS_AREA, >> + .host = (unsigned long)cpuc->ds, >> + .guest = pmu->ds_area, >> + }; >> + >> arr[*nr] = (struct perf_guest_switch_msr){ >> .msr = MSR_IA32_PEBS_ENABLE, >> .host = cpuc->pebs_enabled & ~cpuc->intel_ctrl_guest_mask, > s/pmu/kvm_pmu/ or something. pmu is normally a struct pmu *, and having > it be kvm_pmu here is super confusing. will fix this in V8, Thanks!
diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c index 190d8d98abf0..b336bcaad626 100644 --- a/arch/x86/events/intel/core.c +++ b/arch/x86/events/intel/core.c @@ -21,6 +21,7 @@ #include <asm/intel_pt.h> #include <asm/apic.h> #include <asm/cpu_device_id.h> +#include <asm/kvm_host.h> #include "../perf_event.h" @@ -3915,6 +3916,7 @@ static struct perf_guest_switch_msr *intel_guest_get_msrs(int *nr, void *data) { struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); struct perf_guest_switch_msr *arr = cpuc->guest_switch_msrs; + struct kvm_pmu *pmu = (struct kvm_pmu *)data; u64 intel_ctrl = hybrid(cpuc->pmu, intel_ctrl); u64 pebs_mask = cpuc->pebs_enabled & x86_pmu.pebs_capable; @@ -3945,9 +3947,15 @@ static struct perf_guest_switch_msr *intel_guest_get_msrs(int *nr, void *data) return arr; } - if (!x86_pmu.pebs_vmx) + if (!pmu || !x86_pmu.pebs_vmx) return arr; + arr[(*nr)++] = (struct perf_guest_switch_msr){ + .msr = MSR_IA32_DS_AREA, + .host = (unsigned long)cpuc->ds, + .guest = pmu->ds_area, + }; + arr[*nr] = (struct perf_guest_switch_msr){ .msr = MSR_IA32_PEBS_ENABLE, .host = cpuc->pebs_enabled & ~cpuc->intel_ctrl_guest_mask, diff --git a/arch/x86/include/asm/kvm_host.h b/arch/x86/include/asm/kvm_host.h index 662a0c036ca2..36a3aea8a544 100644 --- a/arch/x86/include/asm/kvm_host.h +++ b/arch/x86/include/asm/kvm_host.h @@ -473,6 +473,7 @@ struct kvm_pmu { DECLARE_BITMAP(all_valid_pmc_idx, X86_PMC_IDX_MAX); DECLARE_BITMAP(pmc_in_use, X86_PMC_IDX_MAX); + u64 ds_area; u64 pebs_enable; u64 pebs_enable_mask; diff --git a/arch/x86/kvm/vmx/pmu_intel.c b/arch/x86/kvm/vmx/pmu_intel.c index 9938b485c31c..5584b8dfadb3 100644 --- a/arch/x86/kvm/vmx/pmu_intel.c +++ b/arch/x86/kvm/vmx/pmu_intel.c @@ -223,6 +223,9 @@ static bool intel_is_valid_msr(struct kvm_vcpu *vcpu, u32 msr) case MSR_IA32_PEBS_ENABLE: ret = vcpu->arch.perf_capabilities & PERF_CAP_PEBS_FORMAT; break; + case MSR_IA32_DS_AREA: + ret = guest_cpuid_has(vcpu, X86_FEATURE_DS); + break; default: ret = get_gp_pmc(pmu, msr, MSR_IA32_PERFCTR0) || get_gp_pmc(pmu, msr, MSR_P6_EVNTSEL0) || @@ -373,6 +376,9 @@ static int intel_pmu_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info) case MSR_IA32_PEBS_ENABLE: msr_info->data = pmu->pebs_enable; return 0; + case MSR_IA32_DS_AREA: + msr_info->data = pmu->ds_area; + return 0; default: if ((pmc = get_gp_pmc(pmu, msr, MSR_IA32_PERFCTR0)) || (pmc = get_gp_pmc(pmu, msr, MSR_IA32_PMC0))) { @@ -441,6 +447,11 @@ static int intel_pmu_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info) return 0; } break; + case MSR_IA32_DS_AREA: + if (is_noncanonical_address(data, vcpu)) + return 1; + pmu->ds_area = data; + return 0; default: if ((pmc = get_gp_pmc(pmu, msr, MSR_IA32_PERFCTR0)) || (pmc = get_gp_pmc(pmu, msr, MSR_IA32_PMC0))) {